genCCall target result_regs args

     CmmComment s -> pure (unitOL (COMMENT (ftext s)))

     CmmTick {} -> pure nilOL

     CmmStore addr src _alignment -> assignMem format addr src

       where

         ty = cmmExprType platform src

   assertVectorRegWidth e

   getRegister' config (ncgPlatform config) e

 assertVectorRegWidth :: CmmExpr -> NatM ()

 assertVectorRegWidth expr = do

   config <- getConfig

   let platform = ncgPlatform config

       mbRegMinBits :: Maybe Int = fromIntegral <$> ncgVectorMinBits config

       format = cmmTypeFormat $ cmmExprType platform expr

 -- | The register width to be used for an operation on the given width

 -- operand.

               format = floatFormat w

           pure $ Any format (\dst -> unitOL $ annExpr expr (MOV (OpReg format dst) op))

         CmmFloat f w -> do

               toWord r = case w of

               format_int = intFormat w

               format_dst = floatFormat w

           intReg <- getNewRegNat format_int

                           expr

                           (MOV (OpReg fmt dst) (OpReg format reg))

                   )

         CmmVec _lits -> pprPanic "getRegister' (CmmLit:CmmVec): " (pdoc plat expr)

         CmmLabel lbl -> do

           let op = OpImm (ImmCLbl lbl)

                 ( Any

                     format

                     ( \dst ->

                             -- We pattern match on the format in the pretty-printer.

                             -- So, we can here simply emit LDRU for all vectors.

                             (LDRU format (OpReg format dst) (OpAddr addr))

         MO_SF_Round from to | from < W32 -> do

           -- extend to the smallest available representation

           (reg_x, code_x) <- signExtendReg from W32 e_reg

           pure

             $ Any

               ( \dst ->

                   e_code

                     `appOL` code_x

               )

         MO_SF_Round from to ->

           let toFmt = floatFormat to

                   fromFmt = intFormat from

                in pure

                     $ Any

                       ( \dst ->

                           e_code

                             `snocOL` annExpr e (MOV (OpReg fromFmt dst) (OpReg fromFmt e_reg))

           reg <- getRegister' config plat e

           addAlignmentCheck align wordWidth reg

         x -> pprPanic ("getRegister' (monadic CmmMachOp): " ++ show x) (pdoc plat expr)

       where

         -- In the case of 16- or 8-bit values we need to sign-extend to 32-bits

           where

             shift = 64 - (widthInBits from - widthInBits to)

           pure $ Any targetFormat $ \dst ->

             code_val

               `snocOL` annExpr

                 expr

                 (VMV (OpReg targetFormat dst) (OpReg format_val reg_val))

     -- Dyadic machops:

     --

     -- The general idea is:

         MO_V_Extract _length w -> vecExtract ((scalarFormatFormat . intScalarFormat) w)

         MO_VF_Add length w -> vecOp (floatVecFormat length w) VADD

         MO_VF_Sub length w -> vecOp (floatVecFormat length w) VSUB

         MO_VF_Mul length w -> vecOp (floatVecFormat length w) VMUL

         MO_VF_Quot length w -> vecOp (floatVecFormat length w) VQUOT

         -- See https://godbolt.org/z/PvcWKMKoW

         MO_VS_Min length w -> vecOp (intVecFormat length w) VSMIN

         MO_VF_Max length w -> vecOp (floatVecFormat length w) VFMAX

         _e -> panic $ "Missing operation " ++ show expr

     -- Generic ternary case.

     CmmMachOp op [x, y, z] ->

       case op of

                     (VMV (OpReg targetFormat dst) (OpReg format_x reg_x))

                   `snocOL` VFMA var (OpReg targetFormat dst) (OpReg format_y reg_y) (OpReg format_z reg_z)

         MO_VF_Insert length width -> vecInsert floatVecFormat length width

         MO_V_Insert length width -> vecInsert intVecFormat length width

         _ ->

                 `snocOL` annExpr

                   expr

                   -- 1. fill elements with index numbers

                   (VID (OpReg format_vid vidReg))

                 `snocOL`

                 VMSEQ (OpReg format_mask v0Reg) (OpReg format_vid vidReg) (OpReg format_idx reg_idx)

                 `snocOL`

                 -- 3. Splat value into tmp vector

 -- fails when the right hand side is forced into a fixed register

 -- (e.g. the result of a call).

 assignMem :: Format -> CmmExpr -> CmmExpr -> NatM InstrBlock

   do

     platform <- getPlatform

     let w = formatToWidth rep

       `consOL` ( code

                    `appOL` addr_code

                    `snocOL` STR rep (OpReg src_format src_reg) (OpAddr addr)

                )

   do

     platform <- getPlatform

     let dst = getRegisterReg platform reg

     MO_SubIntC _w -> unsupported mop

     MO_U_Mul2 _w -> unsupported mop

     MO_VS_Quot {} -> unsupported mop

     MO_VU_Quot {} -> unsupported mop

     MO_VU_Rem {} -> unsupported mop

     MO_I64X2_Min -> unsupported mop

     MO_I64X2_Max -> unsupported mop

       let code = code_fx `appOL` op (OpReg fmt dst) (OpReg format_x reg_fx)

       pure code

 {- Note [RISCV64 far jumps]

 ~~~~~~~~~~~~~~~~~~~~~~~~~~~

       VSUB {} -> 2

       VMUL {} -> 2

       VQUOT {} -> 2

       VSMIN {} -> 2

       VSMAX {} -> 2

       VUMIN {} -> 2

   VMERGE dst op1 op2 opm -> usage (regOp op1 ++ regOp op2 ++ regOp opm, regOp dst)

   VSLIDEDOWN dst op1 op2 -> usage (regOp op1 ++ regOp op2, regOp dst)

   -- WARNING: VSETIVLI is a special case. It changes the interpretation of all vector registers!

   VNEG dst src1 -> usage (regOp src1, regOp dst)

   VADD dst src1 src2 -> usage (regOp src1 ++ regOp src2, regOp dst)

   VSUB dst src1 src2 -> usage (regOp src1 ++ regOp src2, regOp dst)

   VMUL dst src1 src2 -> usage (regOp src1 ++ regOp src2, regOp dst)

   VQUOT dst src1 src2 -> usage (regOp src1 ++ regOp src2, regOp dst)

   VSMIN dst src1 src2 -> usage (regOp src1 ++ regOp src2, regOp dst)

   VSMAX dst src1 src2 -> usage (regOp src1 ++ regOp src2, regOp dst)

   VUMIN dst src1 src2 -> usage (regOp src1 ++ regOp src2, regOp dst)

   where

     toTuple :: Reg -> (Reg, Format)

     toTuple r = (r, format r)

 -- | Apply a given mapping to all the register references in this instruction.

 patchRegsOfInstr :: Instr -> (Reg -> Reg) -> Instr

   VSUB o1 o2 o3 -> VSUB (patchOp o1) (patchOp o2) (patchOp o3)

   VMUL o1 o2 o3 -> VMUL (patchOp o1) (patchOp o2) (patchOp o3)

   VQUOT o1 o2 o3 -> VQUOT (patchOp o1) (patchOp o2) (patchOp o3)

   VSMIN o1 o2 o3 -> VSMIN (patchOp o1) (patchOp o2) (patchOp o3)

   VSMAX o1 o2 o3 -> VSMAX (patchOp o1) (patchOp o2) (patchOp o3)

   VUMIN o1 o2 o3 -> VUMIN (patchOp o1) (patchOp o2) (patchOp o3)

       ]

   where

     fmt'

     mkLdrSpImm imm =

       ANN (text "Reload@" <> int (off - delta))

         $ LDR fmt' (OpReg fmt' reg) (OpAddr (AddrRegImm spMachReg (ImmInt imm)))

   | isFloatFormat fmt = FF64

   | otherwise = II64

 -- | See if this instruction is telling us the current C stack delta

 takeDeltaInstr :: Instr -> Maybe Int

 takeDeltaInstr (ANN _ i) = takeDeltaInstr i

     FCVT FcvtVariant Operand Operand

   | -- | Floating point ABSolute value

     FABS Operand Operand

   | -- | Min

     -- dest = min(r1)

     FMIN Operand Operand Operand

   | -- | Max

     FMAX Operand Operand Operand

   | -- | Floating-point fused multiply-add instructions

     --

     -- - fmadd : d =   r1 * r2 + r3

     -- - fmsub : d = - r1 * r2 + r3

     -- - fnmadd: d = - r1 * r2 - r3

     FMA FMASign Operand Operand Operand Operand

   | -- TODO: Care about the variants (<instr>.x.y) -> sum type

     VMV Operand Operand

   | VID Operand

   | VSUB Operand Operand Operand

   | VMUL Operand Operand Operand

   | VQUOT Operand Operand Operand

   | VSMIN Operand Operand Operand

   | VSMAX Operand Operand Operand

   | VUMIN Operand Operand Operand

   | VFMAX Operand Operand Operand

   | VFMA FMASign Operand Operand Operand

 -- | Operand of a FENCE instruction (@r@, @w@ or @rw@)

 data FenceType = FenceRead | FenceWrite | FenceReadWrite

     VSETIVLI {} -> "VSETIVLI"

     VNEG {} -> "VNEG"

     VADD {} -> "VADD"

     VSUB {} -> "VSUB"

     VMUL {} -> "VMUL"

     VQUOT {} -> "VQUOT"

 d31 = operandFromRegNo FF64 d31RegNo

 fitsIn32bits :: (Num a, Ord a, Bits a) => a -> Bool

 isNbitEncodeable :: Int -> Integer -> Bool

 isNbitEncodeable n i = let shift = n - 1 in (-1 `shiftL` shift) <= i && i < (1 `shiftL` shift)

 isFloatOp :: Operand -> Bool

 isFloatOp op = isFloatRegOp op || isFloatImmOp op

 assertFmtReg :: (HasCallStack) => Format -> Reg -> a -> a

 assertFmtReg fmt reg | fmtRegCombinationIsSane fmt reg = id

 assertFmtReg fmt reg =

 allVectorRegOps :: [Operand] -> Bool

 allVectorRegOps = all isVectorRegOp

     | isFloatOp o1 && isVectorRegOp o2 -> op2 (text "\tvfmv" <> dot <> text "f" <> dot <> text "s") o1 o2

     | isVectorRegOp o1 && isFloatOp o2 -> op2 (text "\tvfmv" <> dot <> opToVInstrSuffix o1 <> dot <> text "f") o1 o2

     | isIntRegOp o1 && isVectorRegOp o2 -> op2 (text "\tvmv" <> dot <> text "x" <> dot <> text "s") o1 o2

     | isVectorRegOp o1 && isIntRegOp o2 -> op2 (text "\tvmv" <> dot <> opToVInstrSuffix o1 <> dot <> text "x") o1 o2

     | isVectorRegOp o1 && isVectorRegOp o2 -> op2 (text "\tvmv" <> dot <> opToVInstrSuffix o1 <> dot <> text "v") o1 o2

     | True -> pprPanic "RV64.pprInstr - impossible vector move (VMV)" (pprOp platform o1 <+> pprOp platform o2 <+> text "fmt" <> colon <> (text . show) fmt)

       <> comma

       <+> pprMasking ma

   VSETIVLI o1 _ _ _ _ _ -> pprPanic "RV64.pprInstr - VSETIVLI wrong operands." (pprOp platform o1)

   VNEG o1 o2 -> pprPanic "RV64.pprInstr - VNEG wrong operands." (pprOps platform [o1, o2])

   VADD o1 o2 o3 -> pprPanic "RV64.pprInstr - VADD wrong operands." (pprOps platform [o1, o2, o3])

   VSUB o1 o2 o3 -> pprPanic "RV64.pprInstr - VSUB wrong operands." (pprOps platform [o1, o2, o3])

   VMUL o1 o2 o3 -> pprPanic "RV64.pprInstr - VMUL wrong operands." (pprOps platform [o1, o2, o3])

   VQUOT o1 o2 o3 | allVectorRegOps [o1, o2, o3] -> op3 (text "\tvfdiv.vv") o1 o2 o3

   VQUOT o1 o2 o3 -> pprPanic "RV64.pprInstr - VQUOT wrong operands." (pprOps platform [o1, o2, o3])

   VSMIN o1 o2 o3 | allVectorRegOps [o1, o2, o3] -> op3 (text "\tvmin.vv") o1 o2 o3

   VSMIN o1 o2 o3 -> pprPanic "RV64.pprInstr - VSMIN wrong operands." (pprOps platform [o1, o2, o3])

   VSMAX o1 o2 o3 | allVectorRegOps [o1, o2, o3] -> op3 (text "\tvmax.vv") o1 o2 o3