where

 import Control.Monad

 import Data.Maybe

 import Data.Word

 import GHC.Cmm

 import GHC.Types.Tickish (GenTickish (..))

 import GHC.Types.Unique.DSM

 import GHC.Utils.Constants (debugIsOn)

 import GHC.Utils.Monad

 import GHC.Utils.Outputable

 import GHC.Utils.Panic

 -- This seems to be PIC compatible; at least `scanelf` (pax-utils) does not

 -- complain.

 -- | Generate jump to jump table target

 --

 -- The index into the jump table is calulated by evaluating @expr@. The

 -- General things for putting together code sequences

 -- | Compute an expression into any register

 getSomeReg expr = do

   r <- getRegister expr

   res@(reg, fmt, _) <- case r of

   pure $ assertFmtReg fmt reg res

 -- | Compute an expression into any floating-point register

 --

 -- If the initial expression is not a floating-point expression, finally move

 -- the result into a floating-point register.

 getFloatReg expr = do

   r <- getRegister expr

   case r of

         MO_AlignmentCheck align wordWidth -> do

           reg <- getRegister' config plat e

           addAlignmentCheck align wordWidth reg

         MO_V_Broadcast length w -> vectorBroadcast (intVecFormat length w) e

         MO_VF_Broadcast length w -> vectorBroadcast (floatVecFormat length w) e

         MO_VS_Neg length w -> vectorNegation (intVecFormat length w)

         MO_VF_Neg length w -> vectorNegation (floatVecFormat length w)

         x -> pprPanic ("getRegister' (monadic CmmMachOp): " ++ show x) (pdoc plat expr)

       where

         -- In the case of 16- or 8-bit values we need to sign-extend to 32-bits

           genericVectorShuffle :: (Int -> Width -> Format) -> Int -> Width -> [Int] -> NatM Register

           genericVectorShuffle toDstFormat length w idxs = do

             -- Our strategy:

             lbl_selVec_v1 <- getNewLabelNat

             lbl_selVec_v2 <- getNewLabelNat

             lbl_mask <- getNewLabelNat

             (reg_y, format_y, code_y) <- getSomeReg y

             let (idxs_v1, idxs_v2) =

                     $ foldl'

                       ( \(acc1, acc2) i ->

                           if i < length then (Just i : acc1, Nothing : acc2) else (Nothing : acc1, Just (i - length) : acc2)

                 -- Finally, the mask must be 0 where v1 should be taken and 1 for v2.

                 -- That's why we do an implicit negation here by focussing on v2.

                 maskVecData = maskData idxs_v2

                 selVecFormat = intVecFormat length w

                 dstFormat = toDstFormat length w

                 addrFormat = intFormat W64

                     VMERGE (OpReg dstFormat dst) (OpReg format_x gathered_x) (OpReg format_y gathered_y) (OpReg maskFormat v0Reg)

                   ]

           selVecData :: Width -> [Maybe Int] -> [CmmStatic]

           selVecData w idxs =

             -- Using the width `w` here is a bit wasteful. But, it saves

         MO_Shl w -> intOp False w (\d x y -> unitOL $ annExpr expr (SLL d x y))

         MO_U_Shr w -> intOp False w (\d x y -> unitOL $ annExpr expr (SRL d x y))

         MO_S_Shr w -> intOp True w (\d x y -> unitOL $ annExpr expr (SRA d x y))

         -- Vector operations

         MO_VF_Extract _length w -> vecExtract ((scalarFormatFormat . floatScalarFormat) w)

         MO_V_Extract _length w -> vecExtract ((scalarFormatFormat . intScalarFormat) w)

     -- Generic ternary case.

     CmmMachOp op [x, y, z] ->

       case op of

         --

         MO_FMA var length w

           | length == 1 ->

               float3Op w (\d n m a -> unitOL $ FMA var d n m a)

               (reg_y, format_y, code_y) <- getSomeReg y

               (reg_z, format_z, code_z) <- getSomeReg z

               let targetFormat = VecFormat length (floatScalarFormat w)

               pure $ Any targetFormat $ \dst ->

                 code_x

                   `appOL` code_y

                   `appOL` code_z

                   `snocOL` annExpr

                     expr

                     (VMV (OpReg targetFormat dst) (OpReg format_x reg_x))

     -- See Note [RISC-V vector C calling convention]

     passArguments _gpRegs _fpRegs [] ((_r, format, _hint, _code_r) : _args) _stackSpaceWords _accumRegs _accumCode

       | isVecFormat format =

     passArguments _ _ _ _ _ _ _ = pprPanic "passArguments" (text "invalid state")

     readResults :: [Reg] -> [Reg] -> [Reg] -> [LocalReg] -> [Reg] -> InstrBlock -> NatM InstrBlock

 import GHC.CmmToAsm.RV64.Regs

 import GHC.CmmToAsm.Types

 import GHC.CmmToAsm.Utils

 import GHC.Platform

 import GHC.Platform.Reg

 import GHC.Prelude hiding (EQ)

 import GHC.Types.Unique (getUnique, pprUniqueAlways)

 import GHC.Utils.Outputable

 import GHC.Utils.Panic

 pprNatCmmDecl :: forall doc. (IsDoc doc) => NCGConfig -> NatCmmDecl RawCmmStatics Instr -> doc

 pprNatCmmDecl config (CmmData section dats) =

         let fma = case variant of

               FMAdd -> text "\tfmadd" <> dot <> floatPrecission d

               FMSub -> text "\tfmsub" <> dot <> floatPrecission d

          in op4 fma d r1 r2 r3

   VFMA variant o1@(OpReg fmt _reg) o2 o3

     | VecFormat _l fmt' <- fmt ->

             fma = case variant of

               FMAdd -> text "madd"

               FMSub -> text "msub" -- TODO: Works only for floats!

          in op3 (tab <> prefix <> fma <> dot <> suffix) o1 o2 o3

   VFMA _variant o1 _o2 _o3 -> pprPanic "RV64.pprInstr - VFMA can only target registers." (pprOp platform o1)

   VMV o1@(OpReg fmt _reg) o2

   VMV o1 o2 -> pprPanic "RV64.pprInstr - invalid VMV instruction" (text "VMV" <+> pprOp platform o1 <> comma <+> pprOp platform o2)

   VID op | isVectorRegOp op -> op1 (text "\tvid.v") op

   VID op -> pprPanic "RV64.pprInstr - VID can only target registers." (pprOp platform op)

   VMSEQ o1 o2 o3 | allVectorRegOps [o1, o2] && isIntOp o3 -> op3 (text "\tvmseq.vx") o1 o2 o3

   VMSEQ o1 o2 o3 -> pprPanic "RV64.pprInstr - VMSEQ wrong operands." (pprOps platform [o1, o2, o3])

   VMERGE o1 o2 o3 o4 | allVectorRegOps [o1, o2, o3, o4] -> op4 (text "\tvmerge.vvm") o1 o2 o3 o4

     # RISC-V: We imply float and double extensions (rv64g), so we only have to

     # check for vector support.

         opts.skip = True

 def ignore_stdout(name, opts):

 test('UnliftedWeakPtr', normal, compile_and_run, [''])

 test('FMA_Primops'

       , when(have_llvm(), extra_ways(["optllvm"]))

       ]

      , compile_and_run, [''])

 test('FMA_ConstantFold'

       , expect_broken(21227)

       , when(have_llvm(), extra_ways(["optllvm"]))

       ]

      [''])

 test('T22710', normal, compile_and_run, [''])

 test('T24496'

       , when(have_llvm(), extra_ways(["optllvm"]))

       ]

     , compile_and_run, ['-O'])

 test('word64x2_basic', [], compile_and_run, [''])

 test('floatx4_arith', [], compile_and_run, [''])

 test('doublex2_arith', [], compile_and_run, [''])

                     , extra_hc_opts('-mfma')

                     ], compile_and_run, [''])

                      , extra_hc_opts('-mfma')

                      ], compile_and_run, [''])

 test('int8x16_arith', [], compile_and_run, [''])