CmmLit lit -> pprLit platform lit

         _other     -> pprExpr1 platform e

 -- Here's the precedence table from GHC.Cmm.Parser:

 -- %nonassoc '>=' '>' '<=' '<' '!=' '=='

 -- %left '|'

 infixMachOp1, infixMachOp7, infixMachOp8 :: MachOp -> Maybe SDoc

 -- %left '-' '+'

 pprExpr7 platform (CmmMachOp (MO_Add rep1) [x, CmmLit (CmmInt i rep2)]) | i < 0

    = pprExpr7 platform x <+> doc <+> pprExpr8 platform y

 pprExpr7 platform e = pprExpr8 platform e

 infixMachOp7 _           = Nothing

 -- %left '/' '*' '%'

    = pprExpr8 platform x <+> doc <+> pprExpr9 platform y

 pprExpr8 platform e = pprExpr9 platform e

 infixMachOp8 _             = Nothing

 pprExpr9 :: Platform -> CmmExpr -> SDoc

   -- Conversions.  Some of these will be NOPs.

   -- Floating-point conversions use the signed variant.

   | MO_FS_Truncate Width Width  -- Float -> Signed int

   | MO_SS_Conv Width Width      -- Signed int -> Signed int

   | MO_UU_Conv Width Width      -- unsigned int -> unsigned int

         = Fixed Format Reg InstrBlock

         | Any   Format (Reg -> InstrBlock)

 -- | Grab the Reg for a CmmReg

 getRegisterReg :: Platform -> CmmReg -> Reg

 getRegisterReg _ (CmmLocal (LocalReg u pk))

   = RegVirtual $ mkVirtualReg u (cmmTypeFormat pk)

   = case globalRegMaybe platform mid of

         Just reg -> RegReal reg

         Nothing  -> pprPanic "getRegisterReg-memory" (ppr $ CmmGlobal reg)

 -- in between operations.

 --

 -- IMPORTANT: this invariant only holds within a single expression tree as

 -- does NOT hold at function entry points or across basic block boundaries,

 -- because the GHC calling convention does not guarantee that callers

 -- zero-extend sub-word arguments. Therefore, any operation that is sensitive

 -- Next we compute `c`: The `%not` requires no extension of its operands, but

 -- we must still truncate the result back down to 8-bits. Finally the `%shrl`

 -- requires no extension and no truncate since we can assume that

 --

 -- TODO:

 --   Don't use Width in Operands

             let w' = opRegWidth w

              in code `snocOL`

                 MVN (OpReg w' dst) (OpReg w' reg) `appOL`

         MO_S_Neg w -> negate code w reg

         MO_F_Neg w -> return $ Any fmt (\dst -> code `snocOL` NEG fmt (OpReg w dst) (OpReg w reg))

           where fmt = intFormat w

         -- Conversions

         -- Vector

         MO_V_Broadcast l w -> return $ Any fmt (\dst -> code `snocOL` DUP fmt (OpReg vw dst) (OpScalarAsVec w reg))

                 code `appOL`

                 code_sx `snocOL`

                 NEG fmt (OpReg w' dst) (OpReg w' reg') `appOL`

         ss_conv from to reg code =

             let w' = opRegWidth (max from to)

                 SBFM (OpReg w' dst) (OpReg w' reg) (OpImm (ImmInt 0)) (toImm (min from to)) `appOL`

                 -- At this point an 8- or 16-bit value would be sign-extended

                 -- to 32-bits. Truncate back down the final width.

     -- Dyadic machops:

     --

                 code_y `appOL`

                 op (OpReg w dst) (OpReg w reg_x) op_y)

           -- In the case of 8- and 16-bit signed arithmetic we must first

           -- sign-extend both arguments to 32-bits.

           -- See Note [Signed arithmetic on AArch64].

               -- compute x<m> <- x

               -- compute x<o> <- y

               -- <OP> x<n>, x<m>, x<o>

               (reg_x, format_x, code_x) <- getSomeReg x

               (op_y, format_y, code_y) <- case y of

                 CmmLit (CmmInt n w)

               massertPpr (isIntFormat format_x && isIntFormat format_y) $ text "intOp: non-int"

               -- This is the width of the registers on which the operation

               -- should be performed.

               return $ Any (intFormat w) $ \dst ->

                   code_x `appOL`

                   code_y `appOL`

                   op (OpReg w' dst) (OpReg w' reg_x) (op_y) `appOL`

           -- A (potentially signed) integer operation.

           -- In the case of 8- and 16-bit signed arithmetic we must first

               -- should be performed.

               let w' = opRegWidth w

                   signExt r

                     | otherwise      = signExtendReg w w' r

               (reg_x_sx, code_x_sx) <- signExt reg_x

               (reg_y_sx, code_y_sx) <- signExt reg_y

                   code_x_sx `appOL`

                   code_y_sx `appOL`

                   op (OpReg w' dst) (OpReg w' reg_x_sx) (OpReg w' reg_y_sx) `appOL`

           floatOp w op = do

             (reg_fx, format_x, code_fx) <- getFloatReg x

         | otherwise -> extend SXTW

       W16           -> extend SXTH

       W8            -> extend SXTB

   where

     noop = return (r, nilOL)

     extend instr = do

         r' <- getNewRegNat (intFormat w')

         return (r', unitOL $ instr (OpReg w' r') (OpReg w r))

       W64 -> nilOL

 -- -----------------------------------------------------------------------------

 --  The 'Amode' type: Memory addressing modes passed up the tree.

                   -- product, and hi gets the overflow (sign extension bits).

                   SMULL (OpReg w' lo) (OpReg W32 reg_a) (OpReg W32 reg_b) `snocOL`

                   ASR (OpReg w' hi) (OpReg w' lo) (OpImm (ImmInt $ widthInBits w)) `appOL`

                   -- CMN (compare negative) tests hi + lo' == 0, i.e. hi == -lo'.

                   -- lo' = LSR(lo, w-1) gives 1 if lo is negative, 0 if positive.

                   -- No overflow iff hi is the sign extension of lo:

                   -- NE to set nd = 1 when overflow occurred.

                   CMN   (OpReg w' hi) (OpRegShift w' lo SLSR (widthInBits w - 1)) `snocOL`

                   CSET  (OpReg w' nd) NE `appOL`

           -- Can't handle > 64 bit operands

           | otherwise -> unsupported (MO_S_Mul2 w)

     PrimTarget (MO_U_Mul2  w)

                       (OpImm (ImmInt $ widthInBits w)) -- lsb

                       (OpImm (ImmInt $ widthInBits w)) -- width to extract

                       `appOL`

                   )

           | otherwise -> unsupported (MO_U_Mul2  w)

     PrimTarget (MO_Clz  w)

     passArguments _ _ _ _ _ _ _ = pprPanic "passArguments" (text "invalid state")

     readResults :: [Reg] -> [Reg] -> [LocalReg] -> [Reg]-> InstrBlock -> NatM (InstrBlock)

     readResults _ _ [] _ accumCode = return accumCode

     readResults [] _ _ _ _ = do

           r_dst = getRegisterReg platform (CmmLocal dst)

       if isFloatFormat format || isVecFormat format

         then readResults (gpReg:gpRegs) fpRegs dsts (fpReg:accumRegs) (accumCode `snocOL` MOV (OpReg w r_dst) (OpReg w fpReg))

     unaryFloatOp w op arg_reg dest_reg = do

       platform <- getPlatform

        when(unregisterised(), skip)],

      multi_compile_and_run,

      ['aarch64-sxtw-run', [('aarch64-sxtw-cmm.cmm', '')], '-O'])