Sven Tennie pushed to branch wip/supersven/riscv-vectors at Glasgow Haskell Compiler / GHC
Commits:
-
f6705fd2
by Sven Tennie at 2025-06-28T17:58:23+02:00
-
463de889
by Sven Tennie at 2025-06-29T12:04:59+02:00
5 changed files:
Changes:
| 1 | -.PHONY: boot configure build test-simd000
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| 2 | - |
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| 3 | -boot:
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| 4 | - ./boot
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| 5 | - |
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| 6 | -configure: boot
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| 7 | - configure_ghc
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| 8 | - |
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| 9 | -build:
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| 10 | - hadrian/build -j --docs=none --flavour=devel2
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| 11 | - |
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| 12 | -test-simd000: build
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| 13 | - CROSS_EMULATOR="qemu-riscv64" hadrian/build -j --docs=none --flavour=devel2 test --only=simd000 |
| 1 | -main.S:
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| 2 | - |
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| 3 | -```
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| 4 | -v8 {q = {0xb0000000000000003}, l = {0x3, 0xb}, w = {0x3, 0x0, 0xb, 0x0}, s = {0x3, 0x0, 0x0, 0x0, 0xb, 0x0, 0x0, 0x0}, b = {0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xb, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}
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| 5 | -v10 {q = {0x1}, l = {0x1, 0x0}, w = {0x1, 0x0, 0x0, 0x0}, s = {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, b = {0x1, 0x0 <repeats 15 times>}}
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| 6 | - |
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| 7 | -``` |
| 1 | -diff --git a/compiler/CodeGen.Platform.h b/compiler/CodeGen.Platform.h
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| 2 | -index 6f85686030..f91fee07fe 100644
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| 3 | ---- a/compiler/CodeGen.Platform.h
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| 4 | -+++ b/compiler/CodeGen.Platform.h
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| 5 | -@@ -1274,44 +1274,6 @@ freeReg REG_XMM5 = False
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| 6 | - freeReg REG_XMM6 = False
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| 7 | - # endif
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| 8 | -
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| 9 | --# if defined(REG_YMM1)
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| 10 | --freeReg REG_YMM1 = False
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| 11 | --# endif
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| 12 | --# if defined(REG_YMM2)
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| 13 | --freeReg REG_YMM2 = False
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| 14 | --# endif
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| 15 | --# if defined(REG_YMM3)
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| 16 | --freeReg REG_YMM3 = False
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| 17 | --# endif
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| 18 | --# if defined(REG_YMM4)
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| 19 | --freeReg REG_YMM4 = False
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| 20 | --# endif
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| 21 | --# if defined(REG_YMM5)
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| 22 | --freeReg REG_YMM5 = False
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| 23 | --# endif
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| 24 | --# if defined(REG_YMM6)
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| 25 | --freeReg REG_YMM6 = False
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| 26 | --# endif
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| 27 | --
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| 28 | --# if defined(REG_ZMM1)
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| 29 | --freeReg REG_ZMM1 = False
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| 30 | --# endif
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| 31 | --# if defined(REG_ZMM2)
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| 32 | --freeReg REG_ZMM2 = False
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| 33 | --# endif
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| 34 | --# if defined(REG_ZMM3)
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| 35 | --freeReg REG_ZMM3 = False
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| 36 | --# endif
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| 37 | --# if defined(REG_ZMM4)
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| 38 | --freeReg REG_ZMM4 = False
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| 39 | --# endif
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| 40 | --# if defined(REG_ZMM5)
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| 41 | --freeReg REG_ZMM5 = False
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| 42 | --# endif
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| 43 | --# if defined(REG_ZMM6)
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| 44 | --freeReg REG_ZMM6 = False
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| 45 | --# endif
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| 46 | --
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| 47 | - freeReg _ = True
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| 48 | -
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| 49 | - #else
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| 50 | -diff --git a/compiler/GHC/CmmToAsm/RV64/Instr.hs b/compiler/GHC/CmmToAsm/RV64/Instr.hs
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| 51 | -index bb4e0ba61c..ec00d5ef68 100644
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| 52 | ---- a/compiler/GHC/CmmToAsm/RV64/Instr.hs
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| 53 | -+++ b/compiler/GHC/CmmToAsm/RV64/Instr.hs
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| 54 | -@@ -20,7 +20,6 @@ import GHC.CmmToAsm.Utils
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| 55 | - import GHC.Data.FastString (LexicalFastString)
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| 56 | - import GHC.Platform
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| 57 | - import GHC.Platform.Reg
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| 58 | --import GHC.Platform.Reg.Class.Separate
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| 59 | - import GHC.Platform.Regs
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| 60 | - import GHC.Prelude
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| 61 | - import GHC.Stack
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| 62 | -diff --git a/compiler/GHC/CmmToAsm/RV64/Ppr.hs b/compiler/GHC/CmmToAsm/RV64/Ppr.hs
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| 63 | -index 75cbcf2da6..2735bb5bef 100644
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| 64 | ---- a/compiler/GHC/CmmToAsm/RV64/Ppr.hs
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| 65 | -+++ b/compiler/GHC/CmmToAsm/RV64/Ppr.hs
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| 66 | -@@ -797,7 +797,7 @@ pprInstr platform instr = case instr of
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| 67 | - FNMSub -> text "\tfnmsub" <> dot <> floatPrecission d
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| 68 | - in op4 fma d r1 r2 r3
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| 69 | - VFMA variant o1@(OpReg fmt _reg) o2 o3
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| 70 | -- | VecFormat l fmt' <- fmt ->
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| 71 | -+ | VecFormat _l fmt' <- fmt ->
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| 72 | - let formatString = if (isFloatFormat . scalarFormatFormat) fmt' then text "f" else text ""
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| 73 | - prefix = text "v" <> formatString
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| 74 | - suffix = text "vv" |
| 1 | -diff --git a/testsuite/driver/cpuinfo.py b/testsuite/driver/cpuinfo.py
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| 2 | -index 4617b04a4c..841ec9dfdc 100644
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| 3 | ---- a/testsuite/driver/cpuinfo.py
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| 4 | -+++ b/testsuite/driver/cpuinfo.py
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| 5 | -@@ -2151,6 +2152,10 @@ def _get_cpu_info_from_riscv_isa():
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| 6 | - seen.add(item)
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| 7 | - return unique_list
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| 8 | - |
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| 9 | -+ # Big endian is easier to head, but RISC-V is little endian
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| 10 | -+ def bigToLittleEndian(w):
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| 11 | -+ return int.from_bytes(w, byteorder='big').to_bytes(4, byteorder='little')
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| 12 | -+
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| 13 | - g_trace.header('Tying to get info from device-tree ...')
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| 14 | - |
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| 15 | - try:
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| 16 | -@@ -2175,16 +2180,17 @@ def _get_cpu_info_from_riscv_isa():
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| 17 | - |
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| 18 | - if arch_string.startswith('rv32'):
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| 19 | - vlen = run_asm(
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| 20 | -- b"\xc2\x20\x25\x73", # csrr a0, 0xc22
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| 21 | -- b"\x00\x00\x80\x67" # ret
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| 22 | -+ bigToLittleEndian(b"\xc2\x20\x25\x73"), # csrr a0, 0xc22
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| 23 | -+ bigToLittleEndian(b"\x00\x00\x80\x67") # ret
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| 24 | - )
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| 25 | - elif arch_string.startswith('rv64'):
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| 26 | - vlen = run_asm(
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| 27 | -- b"\xc2\x20\x25\x73", # csrr a0, 0xc22
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| 28 | -- b"\x00\x05\x05\x1b", # sext.w a0, a0
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| 29 | -- b"\x00\x00\x80\x67" # ret
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| 30 | -+ bigToLittleEndian(b"\xc2\x20\x25\x73"), # csrr a0, 0xc22
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| 31 | -+ bigToLittleEndian(b"\x00\x05\x05\x1b"), # sext.w a0, a0
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| 32 | -+ bigToLittleEndian(b"\x00\x00\x80\x67") # ret
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| 33 | - ) |
| ... | ... | @@ -4,10 +4,17 @@ |
| 4 | 4 | #if defined(__riscv_v) && defined(__riscv_v_intrinsic)
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| 5 | 5 | #include <riscv_vector.h>
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| 6 | 6 | #include <stdlib.h>
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| 7 | +#include <signal.h>
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| 8 | +#include <setjmp.h>
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| 7 | 9 | |
| 8 | -// TODO: Find better file for this.
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| 9 | -void* malloc_vlen_vector() {
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| 10 | - return malloc(__riscv_vlenb());
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| 10 | +static jmp_buf jmpbuf;
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| 11 | + |
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| 12 | +// Signal handler for SIGILL (Illegal Instruction)
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| 13 | +static void sigill_handler(int);
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| 14 | +static void sigill_handler(__attribute__((unused)) int sig) {
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| 15 | + // If we get here, the vector instruction caused an illegal instruction
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| 16 | + // exception. We just swallow it.
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| 17 | + longjmp(jmpbuf, 1);
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| 11 | 18 | }
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| 12 | 19 | #endif
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| 13 | 20 | |
| ... | ... | @@ -74,11 +81,29 @@ int checkVectorSupport(void) { |
| 74 | 81 | supports_V32 = hwcap & PPC_FEATURE_HAS_VSX;
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| 75 | 82 | */
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| 76 | 83 | |
| 84 | + // Detect RISC-V support
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| 77 | 85 | #elif defined(__riscv_v) && defined(__riscv_v_intrinsic)
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| 78 | 86 | // __riscv_v ensures we only get here when the compiler target (arch)
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| 79 | 87 | // supports vectors.
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| 80 | - |
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| 81 | - unsigned vlenb = __riscv_vlenb();
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| 88 | + // Unfortunately, the status registers that could tell about RVV support
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| 89 | + // are part of the priviledged ISA. So, we try to get VLENB from the `vlenb`
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| 90 | + // register that only exists with RVV. If this throws an illegal instruction
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| 91 | + // exception, we know that RVV is not supported by the executing CPU.
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| 92 | + |
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| 93 | + // Set up signal handler to catch illegal instruction
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| 94 | + struct sigaction sa, old_sa;
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| 95 | + sa.sa_handler = sigill_handler;
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| 96 | + sigemptyset(&sa.sa_mask);
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| 97 | + sa.sa_flags = 0;
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| 98 | + sigaction(SIGILL, &sa, &old_sa);
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| 99 | +
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| 100 | + unsigned vlenb = 0;
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| 101 | + if (setjmp(jmpbuf) == 0) {
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| 102 | + // Try to execute a vector instruction
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| 103 | + vlenb = __riscv_vlenb();
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| 104 | + }
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| 105 | + // Restore original signal handler
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| 106 | + sigaction(SIGILL, &old_sa, NULL);
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| 82 | 107 | |
| 83 | 108 | // VLENB gives the length in bytes
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| 84 | 109 | supports_V16 = vlenb >= 16;
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