Sven Tennie pushed to branch wip/supersven/riscv-vectors at Glasgow Haskell Compiler / GHC
Commits:
-
2306dd0a
by Sven Tennie at 2025-07-02T18:06:29+02:00
-
80263d35
by Sven Tennie at 2025-07-02T18:10:13+02:00
5 changed files:
- configure.ac
- libraries/unix
- + m4/fp_riscv_march.m4
- rts/CheckVectorSupport.c
- utils/ghc-toolchain/src/GHC/Toolchain/Tools/Cc.hs
Changes:
| ... | ... | @@ -450,6 +450,8 @@ FP_SET_CFLAGS_C99([CC_STAGE0],[CONF_CC_OPTS_STAGE0],[CONF_CPP_OPTS_STAGE0]) |
| 450 | 450 | FP_SET_CFLAGS_C99([CC],[CONF_CC_OPTS_STAGE1],[CONF_CPP_OPTS_STAGE1])
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| 451 | 451 | FP_SET_CFLAGS_C99([CC],[CONF_CC_OPTS_STAGE2],[CONF_CPP_OPTS_STAGE2])
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| 452 | 452 | |
| 453 | +FP_RISCV_MARCH([CONF_CC_OPTS_STAGE2])
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|
| 454 | + |
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| 453 | 455 | dnl ** Do we have a compatible emsdk version?
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| 454 | 456 | dnl --------------------------------------------------------------
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| 455 | 457 | EMSDK_VERSION("3.1.20", "", "")
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| 1 | -Subproject commit 74ae1c0d9dd1518434f7d6cd3e63d7769599e0f9 |
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| 1 | +Subproject commit 47d5fc4a8f19207819030725e7de23c65fa61a04 |
| 1 | +dnl --------------------------------------------------------------------------
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|
| 2 | +dnl Set RISC-V architecture with vector extension (RVV)
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| 3 | +dnl
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| 4 | +dnl This macro checks if the target is RISC-V and if so, sets -march=rv64gcv /
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| 5 | +dnl -march=rv32gcv (general, compressed, vector) to enable vector extension
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| 6 | +dnl --------------------------------------------------------------------------
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| 7 | + |
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| 8 | +# FP_RISCV_MARCH(compiler_flags_var)
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| 9 | +# ------------------------------------------
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| 10 | +#
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| 11 | +# Example usage:
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| 12 | +# FP_RISCV_MARCH([CONF_CC_OPTS_STAGE2])
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| 13 | +#
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| 14 | +AC_DEFUN([FP_RISCV_MARCH],
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| 15 | +[
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| 16 | + AC_REQUIRE([AC_CANONICAL_TARGET])
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| 17 | + |
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| 18 | + # Check if target is RISC-V
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|
| 19 | + case "$target" in
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| 20 | + riscv64*-*-*)
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| 21 | + AC_MSG_NOTICE([add -march=rv64gcv to $1])
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| 22 | + |
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| 23 | + # Add vector extension flag to the specified variable
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| 24 | + $1="$$1 -march=rv64gcv"
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|
| 25 | + ;;
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| 26 | +
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| 27 | + riscv32*-*-*)
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| 28 | + AC_MSG_NOTICE([add -march=rv64gcv to $1])
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| 29 | + |
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| 30 | + # Add vector extension flag to the specified variable
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| 31 | + $1="$$1 -march=rv32gcv"
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| 32 | + ;;
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|
| 33 | + esac
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|
| 34 | +]) |
| ... | ... | @@ -14,7 +14,7 @@ static void sigill_handler(int); |
| 14 | 14 | static void sigill_handler(__attribute__((unused)) int sig) {
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| 15 | 15 | // If we get here, the vector instruction caused an illegal instruction
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| 16 | 16 | // exception. We just swallow it.
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| 17 | - longjmp(jmpbuf, 1);
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| 17 | + siglongjmp(jmpbuf, 1);
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| 18 | 18 | }
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| 19 | 19 | #endif
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| 20 | 20 | |
| ... | ... | @@ -98,9 +98,9 @@ int checkVectorSupport(void) { |
| 98 | 98 | sigaction(SIGILL, &sa, &old_sa);
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| 99 | 99 |
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| 100 | 100 | unsigned vlenb = 0;
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| 101 | - if (setjmp(jmpbuf) == 0) {
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| 101 | + if (sigsetjmp(jmpbuf, 1) == 0) {
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| 102 | 102 | // Try to execute a vector instruction
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| 103 | - vlenb = __riscv_vlenb();
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| 103 | + asm volatile("csrr %0, vlenb" : "=r" (vlenb) :: "memory");
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| 104 | 104 | }
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| 105 | 105 | // Restore original signal handler
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| 106 | 106 | sigaction(SIGILL, &old_sa, NULL);
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| ... | ... | @@ -176,6 +176,8 @@ addPlatformDepCcFlags archOs cc0 = do |
| 176 | 176 | -- On LoongArch64, we need `-mcmodel=medium` to tell gcc to generate big
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| 177 | 177 | -- enough jump instruction.
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| 178 | 178 | return $ cc1 & _ccFlags %++ "-mcmodel=medium"
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| 179 | + ArchOS ArchRISCV64 _ ->
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| 180 | + return $ cc1 & _ccFlags %++ "-march=rv64gcv"
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| 179 | 181 | _ ->
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| 180 | 182 | return cc1
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| 181 | 183 |