Marge Bot pushed to branch master at Glasgow Haskell Compiler / GHC
Commits:
-
89e8ff3d
by Peng Fan at 2025-09-23T20:42:37-04:00
3 changed files:
- compiler/GHC/CmmToAsm/LA64/CodeGen.hs
- compiler/GHC/CmmToAsm/LA64/Instr.hs
- compiler/GHC/CmmToAsm/LA64/Ppr.hs
Changes:
| ... | ... | @@ -1805,6 +1805,49 @@ genCCall target dest_regs arg_regs = do |
| 1805 | 1805 | where
|
| 1806 | 1806 | shift = (widthToInt w)
|
| 1807 | 1807 | |
| 1808 | + PrimTarget (MO_BSwap w)
|
|
| 1809 | + | w `elem` [W16, W32, W64],
|
|
| 1810 | + [arg_reg] <- arg_regs,
|
|
| 1811 | + [dest_reg] <- dest_regs -> do
|
|
| 1812 | + platform <- getPlatform
|
|
| 1813 | + (reg_x, _, code_x) <- getSomeReg arg_reg
|
|
| 1814 | + let dst_reg = getRegisterReg platform (CmmLocal dest_reg)
|
|
| 1815 | + case w of
|
|
| 1816 | + W64 -> return ( code_x `appOL` toOL
|
|
| 1817 | + [
|
|
| 1818 | + REVBD (OpReg w dst_reg) (OpReg w reg_x)
|
|
| 1819 | + ])
|
|
| 1820 | + W32 -> return ( code_x `appOL` toOL
|
|
| 1821 | + [
|
|
| 1822 | + REVB2W (OpReg w dst_reg) (OpReg w reg_x)
|
|
| 1823 | + ])
|
|
| 1824 | + _ -> return ( code_x `appOL` toOL
|
|
| 1825 | + [
|
|
| 1826 | + REVB2H (OpReg w dst_reg) (OpReg w reg_x)
|
|
| 1827 | + ])
|
|
| 1828 | + | otherwise -> unsupported (MO_BSwap w)
|
|
| 1829 | + |
|
| 1830 | + PrimTarget (MO_BRev w)
|
|
| 1831 | + | w `elem` [W8, W16, W32, W64],
|
|
| 1832 | + [arg_reg] <- arg_regs,
|
|
| 1833 | + [dest_reg] <- dest_regs -> do
|
|
| 1834 | + platform <- getPlatform
|
|
| 1835 | + (reg_x, _, code_x) <- getSomeReg arg_reg
|
|
| 1836 | + let dst_reg = getRegisterReg platform (CmmLocal dest_reg)
|
|
| 1837 | + case w of
|
|
| 1838 | + W8 -> return ( code_x `appOL` toOL
|
|
| 1839 | + [
|
|
| 1840 | + BITREV4B (OpReg W32 reg_x) (OpReg W32 reg_x),
|
|
| 1841 | + AND (OpReg W64 dst_reg) (OpReg W64 reg_x) (OpImm (ImmInt 255))
|
|
| 1842 | + ])
|
|
| 1843 | + W16 -> return ( code_x `appOL` toOL
|
|
| 1844 | + [
|
|
| 1845 | + BITREV (OpReg W64 reg_x) (OpReg W64 reg_x),
|
|
| 1846 | + SRL (OpReg W64 dst_reg) (OpReg W64 reg_x) (OpImm (ImmInt 48))
|
|
| 1847 | + ])
|
|
| 1848 | + _ -> return ( code_x `snocOL` BITREV (OpReg w dst_reg) (OpReg w reg_x))
|
|
| 1849 | + | otherwise -> unsupported (MO_BRev w)
|
|
| 1850 | + |
|
| 1808 | 1851 | -- mop :: CallishMachOp (see GHC.Cmm.MachOp)
|
| 1809 | 1852 | PrimTarget mop -> do
|
| 1810 | 1853 | -- We'll need config to construct forien targets
|
| ... | ... | @@ -1939,8 +1982,6 @@ genCCall target dest_regs arg_regs = do |
| 1939 | 1982 | MO_PopCnt w -> mkCCall (popCntLabel w)
|
| 1940 | 1983 | MO_Pdep w -> mkCCall (pdepLabel w)
|
| 1941 | 1984 | MO_Pext w -> mkCCall (pextLabel w)
|
| 1942 | - MO_BSwap w -> mkCCall (bSwapLabel w)
|
|
| 1943 | - MO_BRev w -> mkCCall (bRevLabel w)
|
|
| 1944 | 1985 | |
| 1945 | 1986 | -- or a possibly side-effecting machine operation
|
| 1946 | 1987 | mo@(MO_AtomicRead w ord)
|
| ... | ... | @@ -126,8 +126,7 @@ regUsageOfInstr platform instr = case instr of |
| 126 | 126 | REVHD dst src1 -> usage (regOp src1, regOp dst)
|
| 127 | 127 | BITREV4B dst src1 -> usage (regOp src1, regOp dst)
|
| 128 | 128 | BITREV8B dst src1 -> usage (regOp src1, regOp dst)
|
| 129 | - BITREVW dst src1 -> usage (regOp src1, regOp dst)
|
|
| 130 | - BITREVD dst src1 -> usage (regOp src1, regOp dst)
|
|
| 129 | + BITREV dst src1 -> usage (regOp src1, regOp dst)
|
|
| 131 | 130 | BSTRINS _ dst src1 src2 src3 -> usage (regOp src1 ++ regOp src2 ++ regOp src3, regOp dst)
|
| 132 | 131 | BSTRPICK _ dst src1 src2 src3 -> usage (regOp src1 ++ regOp src2 ++ regOp src3, regOp dst)
|
| 133 | 132 | MASKEQZ dst src1 src2 -> usage (regOp src1 ++ regOp src2, regOp dst)
|
| ... | ... | @@ -309,8 +308,7 @@ patchRegsOfInstr instr env = case instr of |
| 309 | 308 | REVHD o1 o2 -> REVHD (patchOp o1) (patchOp o2)
|
| 310 | 309 | BITREV4B o1 o2 -> BITREV4B (patchOp o1) (patchOp o2)
|
| 311 | 310 | BITREV8B o1 o2 -> BITREV8B (patchOp o1) (patchOp o2)
|
| 312 | - BITREVW o1 o2 -> BITREVW (patchOp o1) (patchOp o2)
|
|
| 313 | - BITREVD o1 o2 -> BITREVD (patchOp o1) (patchOp o2)
|
|
| 311 | + BITREV o1 o2 -> BITREV (patchOp o1) (patchOp o2)
|
|
| 314 | 312 | BSTRINS f o1 o2 o3 o4 -> BSTRINS f (patchOp o1) (patchOp o2) (patchOp o3) (patchOp o4)
|
| 315 | 313 | BSTRPICK f o1 o2 o3 o4 -> BSTRPICK f (patchOp o1) (patchOp o2) (patchOp o3) (patchOp o4)
|
| 316 | 314 | MASKEQZ o1 o2 o3 -> MASKEQZ (patchOp o1) (patchOp o2) (patchOp o3)
|
| ... | ... | @@ -700,8 +698,7 @@ data Instr |
| 700 | 698 | | REVHD Operand Operand
|
| 701 | 699 | | BITREV4B Operand Operand
|
| 702 | 700 | | BITREV8B Operand Operand
|
| 703 | - | BITREVW Operand Operand
|
|
| 704 | - | BITREVD Operand Operand
|
|
| 701 | + | BITREV Operand Operand
|
|
| 705 | 702 | | BSTRINS Format Operand Operand Operand Operand
|
| 706 | 703 | | BSTRPICK Format Operand Operand Operand Operand
|
| 707 | 704 | | MASKEQZ Operand Operand Operand
|
| ... | ... | @@ -824,8 +821,7 @@ instrCon i = |
| 824 | 821 | REVHD{} -> "REVHD"
|
| 825 | 822 | BITREV4B{} -> "BITREV4B"
|
| 826 | 823 | BITREV8B{} -> "BITREV8B"
|
| 827 | - BITREVW{} -> "BITREVW"
|
|
| 828 | - BITREVD{} -> "BITREVD"
|
|
| 824 | + BITREV{} -> "BITREV"
|
|
| 829 | 825 | BSTRINS{} -> "BSTRINS"
|
| 830 | 826 | BSTRPICK{} -> "BSTRPICK"
|
| 831 | 827 | MASKEQZ{} -> "MASKEQZ"
|
| ... | ... | @@ -802,8 +802,9 @@ pprInstr platform instr = case instr of |
| 802 | 802 | -- BITREV.{W/D}
|
| 803 | 803 | BITREV4B o1 o2 -> op2 (text "\tbitrev.4b") o1 o2
|
| 804 | 804 | BITREV8B o1 o2 -> op2 (text "\tbitrev.8b") o1 o2
|
| 805 | - BITREVW o1 o2 -> op2 (text "\tbitrev.w") o1 o2
|
|
| 806 | - BITREVD o1 o2 -> op2 (text "\tbitrev.d") o1 o2
|
|
| 805 | + BITREV o1 o2
|
|
| 806 | + | OpReg W32 _ <- o2 -> op2 (text "\tbitrev.w") o1 o2
|
|
| 807 | + | OpReg W64 _ <- o2 -> op2 (text "\tbitrev.d") o1 o2
|
|
| 807 | 808 | -- BSTRINS.{W/D}
|
| 808 | 809 | BSTRINS II64 o1 o2 o3 o4 -> op4 (text "\tbstrins.d") o1 o2 o3 o4
|
| 809 | 810 | BSTRINS II32 o1 o2 o3 o4 -> op4 (text "\tbstrins.w") o1 o2 o3 o4
|