2018-05-06 16:41 GMT+02:00 Andreas Klebinger <klebinger.andreas@gmx.at>:

[...] If we only consider 16byte (DSB Buffer) and 32 Byte (Cache Lines) relevant this reduces the possibilities by a lot after all. [...]

Nitpick: Cache lines on basically all Intel/AMD processors contain 64 bytes, see e.g. http://www.agner.org/optimize/microarchitecture.pdf