Yeah, I do like how the 7.8 calling convention allows up to 6 Double args to go in registers.

Thats a good idea actually,

so it'd be adding


  // Pass in STG registers for  128bit simd vectors
  CCIfType<[ v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
            CCIfSubtarget<"hasSSE1()",
            CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>,

// Pass in STG registers for first 7  256bit simd vectors
CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
                          CCIfSubtarget<"hasAVX()",
                          CCAssignToReg<[YMM0, YMM1, YMM2, YMM3,
                                         YMM4, YMM5, YMM6]>>>

to the X86_32 convention then. so floats and doubles would still be spilled to stack, but SIMD (short vectors) could use the registers as applicable.

That would preserve calling convention compatibility, but still allow adding SIMD to 32bit x86.

If that'd be kosher / looks good, please indicate so on the ghc trac ticket, so i can fold this into the patch on the llvm-commits list post haste. Would rather not have it be a whole separate patch

On Mon, Jul 8, 2013 at 6:22 PM, Geoffrey Mainland <mainland@apeiron.net> wrote:

We would like code compiled with the LLVM back-end that doesn't use SIMD
vectors to inter-operate with code compiled with the native codegen. The
native codegen passes floating point arguments on the stack, so if we
changed the GHC LLVM calling convention to pass Floats and Doubles in
registers, we would need to change the native codegen to do the same.

Or are you suggesting that we only pass SIMD short-vectors in the xmm
registers on x86?

I changed the calling convention (for both back-ends) when I did the
SIMD work. It was a lucky accident that I didn't have to patch LLVM.

Geoff

On 07/08/2013 07:57 PM, Carter Schonwald wrote:
> Hey All,
> Is there any reasons *not* to add SSE / AVX register support to the
llvm 32 bit x86 ghc calling convention? It looks like (as with x86_64)
that adding additional simd registers to the calling convention would be
fully backwards compatible with current ghc approach to 32bit function
calls, but would allow ghc 32bit (at some future point) to have decent
floating point performance when applicable.
>
> I'm ok either way, but would be helpful to get some opinions.
>
> just to recap, i'm working on getting a patch sorted out for adding
AVX support to the ghc x86_64 LLVM calling convention
http://ghc.haskell.org/trac/ghc/ticket/8033, and now would be a good
time to add anything to the 32bit x86 calling convention
>
> thanks
> -Carter