Sven Tennie pushed to branch wip/supersven/riscv-vectors at Glasgow Haskell Compiler / GHC Commits: 33e352cf by Sven Tennie at 2025-07-27T12:42:55+02:00 Introduce -mriscv-vlen driver argument with runtime check Ensure that the configured vlen fits to the detected one. Docs version - - - - - c222800f by Sven Tennie at 2025-07-27T12:42:55+02:00 Compile AutoApply_V*.cmm and Jumps_V*.cmm with vector support If the running CPU does not support RVV, this code will not be executed. However, at build time, we have to emit (prepare) it. - - - - - 1109dbad by Sven Tennie at 2025-07-27T12:42:55+02:00 RV64: Emit code for vector extension (RVV) This includes adding the vector registers to the register allocator and adding support for the related MachOps to the native code generator. Also, fix FMA support while implementing vector FMA. - - - - - a2379744 by Sven Tennie at 2025-07-27T12:42:55+02:00 point free: floatVecFormat & intVecFormat Drive-by refactoring. - - - - - 86586e06 by Sven Tennie at 2025-07-27T12:42:55+02:00 RV64: Detect RVV CPU features and make them configurable for CROSS_EMULATOR Unfortunately, the cpuinfo Python package is abandonned. Thus, we just add RVV detection here (and not upstream.) cpuinfo is not executed on the CROSS_EMULATOR. So, we make supported features configurable. Also, adjust the related testlib functions to cover RISC-V. And, use them in tests. - - - - - 2d39200f by Sven Tennie at 2025-07-27T12:42:55+02:00 Test for the RVV (RISC-V vectors) C calling convention This could be enhanced to cover other architectures as well. - - - - - 2d46b39d by Sven Tennie at 2025-07-27T12:42:55+02:00 RV64: Always configure -march=rv64gcv Independent of if RVV is supported by the executing processor, we need to be able to compile code for it. - - - - - addc1856 by Sven Tennie at 2025-07-27T12:42:55+02:00 RV64: Check for GCC >= 14 in autoconf Older versions use another (obsolete) C calling convention. So, we must limit ourselves here to newer GCCs. - - - - - 522214d0 by Sven Tennie at 2025-07-27T12:42:55+02:00 RV64: Test and fix (V)FMA Use the testlib predicate to reduce code duplications. - - - - - 42 changed files: - compiler/CodeGen.Platform.h - compiler/GHC/Cmm/CallConv.hs - compiler/GHC/CmmToAsm/Config.hs - compiler/GHC/CmmToAsm/Format.hs - compiler/GHC/CmmToAsm/RV64.hs - compiler/GHC/CmmToAsm/RV64/CodeGen.hs - compiler/GHC/CmmToAsm/RV64/Instr.hs - compiler/GHC/CmmToAsm/RV64/Ppr.hs - compiler/GHC/CmmToAsm/RV64/Regs.hs - compiler/GHC/CmmToAsm/Reg/Graph/TrivColorable.hs - compiler/GHC/CmmToAsm/Reg/Linear.hs - compiler/GHC/CmmToAsm/Reg/Linear/RV64.hs - compiler/GHC/Driver/Config/CmmToAsm.hs - compiler/GHC/Driver/Config/StgToCmm.hs - compiler/GHC/Driver/DynFlags.hs - compiler/GHC/Driver/Session.hs - compiler/GHC/Linker/ExtraObj.hs - compiler/GHC/Platform/Reg/Class.hs - compiler/GHC/StgToCmm/Config.hs - compiler/GHC/StgToCmm/Prim.hs - compiler/GHC/Utils/Outputable.hs - configure.ac - distrib/configure.ac.in - docs/users_guide/using.rst - hadrian/src/Settings/Packages.hs - + m4/fp_riscv_check_gcc_version.m4 - + m4/fp_riscv_march.m4 - rts/CheckVectorSupport.c - rts/RtsStartup.c - rts/include/stg/MachRegs.h - rts/include/stg/MachRegs/riscv64.h - testsuite/driver/cpu_features.py - testsuite/driver/cpuinfo.py - testsuite/driver/testglobals.py - testsuite/driver/testlib.py - testsuite/tests/primops/should_run/all.T - + testsuite/tests/simd/should_run/VectorCCallConv.hs - + testsuite/tests/simd/should_run/VectorCCallConv.stdout - + testsuite/tests/simd/should_run/VectorCCallConv_c.c - testsuite/tests/simd/should_run/all.T - testsuite/tests/simd/should_run/simd013C.c - utils/ghc-toolchain/src/GHC/Toolchain/Tools/Cc.hs The diff was not included because it is too large. View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/compare/7decf40aa5b9e5ab9d8c17ef17c8f62... -- View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/compare/7decf40aa5b9e5ab9d8c17ef17c8f62... You're receiving this email because of your account on gitlab.haskell.org.