Marge Bot pushed to branch wip/marge_bot_batch_merge_job at Glasgow Haskell Compiler / GHC Commits: d99f8326 by Cheng Shao at 2025-12-11T19:14:18-05:00 compiler: remove unused CPP code in foreign stub This patch removes unused CPP code in the generated foreign stub: - `#define IN_STG_CODE 0` is not needed, since `Rts.h` already includes this definition - The `if defined(__cplusplus)` code paths are not needed in the `.c` file, since we don't generate C++ stubs and don't include C++ headers in our stubs. But it still needs to be present in the `.h` header since it might be later included into C++ source files. - - - - - 46c9746f by Cheng Shao at 2025-12-11T19:14:57-05:00 configure: bump LlvmMaxVersion to 22 This commit bumps LlvmMaxVersion to 22; 21.x releases have been available since Aug 26th, 2025 and there's no regressions with 21.x so far. This bump is also required for updating fedora image to 43. - - - - - 96fce8d0 by Cheng Shao at 2025-12-12T01:17:51+01:00 hadrian: add support for building with UndefinedBehaviorSanitizer This patch adds a +ubsan flavour transformer to hadrian to build all stage1+ C/C++ code with UndefinedBehaviorSanitizer. This is particularly useful to catch potential undefined behavior in the RTS codebase. - - - - - f7a06d8c by Cheng Shao at 2025-12-12T01:17:51+01:00 ci: update alpine/fedora & add ubsan job This patch updates alpine image to 3.23, fedora image to 43, and adds a `x86_64-linux-fedora43-validate+debug_info+ubsan` job that's run in validate/nightly pipelines to catch undefined behavior in the RTS codebase. - - - - - 2ccd11ca by Cheng Shao at 2025-12-12T01:17:51+01:00 rts: fix zero-length VLA undefined behavior in interpretBCO This commit fixes a zero-length VLA undefined behavior in interpretBCO, caught by UBSan: ``` +rts/Interpreter.c:3133:19: runtime variable length array bound evaluates to non-positive value 0 ``` - - - - - 4156ed19 by Cheng Shao at 2025-12-12T01:17:51+01:00 rts: fix unaligned ReadSpB in interpretBCO This commit fixes unaligned ReadSpB in interpretBCO, caught by UBSan: ``` +rts/Interpreter.c:2174:64: runtime load of misaligned address 0x004202059dd1 for type 'StgWord', which requires 8 byte alignment ``` To perform proper unaligned read, we define StgUnalignedWord as a type alias of StgWord with aligned(1) attribute, and load StgUnalignedWord instead of StgWord in ReadSpB, so the C compiler is aware that we're not loading with natural alignment. - - - - - fef89fb9 by Cheng Shao at 2025-12-12T01:17:51+01:00 rts: fix signed integer overflow in subword arithmetic in interpretBCO This commit fixes signed integer overflow in subword arithmetic in interpretBCO, see added note for detailed explanation. - - - - - 2a5bc4ba by sheaf at 2025-12-12T02:56:17-05:00 X86 CodeGen: fix assign_eax_sse_regs We must set %al to the number of SSE2 registers that contain arguments (in case we are dealing with a varargs function). The logic for counting how many arguments reside in SSE2 registers was incorrect, as it used 'isFloatFormat', which incorrectly ignores vector registers. We now instead do case analysis on the register class: is_sse_reg r = case targetClassOfReg platform r of RcFloatOrVector -> True RcInteger -> False This change is necessary to prevent segfaults in T20030_test1j, because subsequent commits change the format calculations, resulting in vector formats more often. - - - - - feb9b195 by sheaf at 2025-12-12T02:56:17-05:00 Liveness analysis: consider register formats This commit updates the register allocator to be a bit more careful in situations in which a single register is used at multiple different formats, e.g. when xmm1 is used both to store a Double# and a DoubleX2#. This is done by introducing the 'Regs' newtype around 'UniqSet RegWithFormat', for which the combining operations take the larger of the two formats instead of overriding the format. Operations on 'Regs' are defined in 'GHC.CmmToAsm.Reg.Regs'. There is a modest compile-time cost for the additional overhead for tracking register formats, which causes the metric increases of this commit. The subtle aspects of the implementation are outlined in Note [Register formats in liveness analysis] in GHC.CmmToAsm.Reg.Liveness. Fixes #26411 #26611 ------------------------- Metric Increase: T12707 T26425 T3294 ------------------------- - - - - - 36ee30f3 by sheaf at 2025-12-12T02:56:17-05:00 Register allocator: reload at same format as spill This commit ensures that if we spill a register onto the stack at a given format, we then always reload the register at this same format. This ensures we don't end up in a situation where we spill F64x2 but end up only reloading the lower F64. This first reload would make us believe the whole data is in a register, thus silently losing the upper 64 bits of the spilled register's contents. Fixes #26526 - - - - - 02c25c49 by sheaf at 2025-12-12T02:56:17-05:00 Register allocation: writes redefine format As explained in Note [Allocated register formats] in GHC.CmmToAsm.Reg.Linear, we consider all writes to redefine the format of the register. This ensures that in a situation such as movsd .Ln6m(%rip),%v1 shufpd $0,%v1,%v1 we properly consider the broadcast operation to change the format of %v1 from F64 to F64x2. This completes the fix to #26411 (test in T26411b). - - - - - 35 changed files: - .gitlab-ci.yml - .gitlab/generate-ci/gen_ci.hs - .gitlab/jobs.yaml - .gitlab/rel_eng/fetch-gitlab-artifacts/fetch_gitlab.py - .gitlab/rel_eng/mk-ghcup-metadata/mk_ghcup_metadata.py - compiler/GHC/CmmToAsm/Reg/Graph.hs - compiler/GHC/CmmToAsm/Reg/Graph/Coalesce.hs - compiler/GHC/CmmToAsm/Reg/Graph/Spill.hs - compiler/GHC/CmmToAsm/Reg/Graph/SpillCost.hs - compiler/GHC/CmmToAsm/Reg/Linear.hs - compiler/GHC/CmmToAsm/Reg/Linear/Base.hs - compiler/GHC/CmmToAsm/Reg/Linear/JoinToTargets.hs - compiler/GHC/CmmToAsm/Reg/Liveness.hs - + compiler/GHC/CmmToAsm/Reg/Regs.hs - compiler/GHC/CmmToAsm/Reg/Target.hs - compiler/GHC/CmmToAsm/X86/CodeGen.hs - compiler/GHC/CmmToAsm/X86/Instr.hs - compiler/GHC/Driver/CodeOutput.hs - compiler/GHC/Types/Unique/FM.hs - compiler/GHC/Types/Unique/Set.hs - compiler/ghc.cabal.in - configure.ac - hadrian/doc/flavours.md - hadrian/src/Flavour.hs - + rts/.ubsan-suppressions - rts/Interpreter.c - rts/include/stg/Types.h - rts/rts.cabal - testsuite/driver/testglobals.py - testsuite/driver/testlib.py - + testsuite/tests/simd/should_run/T26411.hs - + testsuite/tests/simd/should_run/T26411.stdout - + testsuite/tests/simd/should_run/T26411b.hs - + testsuite/tests/simd/should_run/T26411b.stdout - testsuite/tests/simd/should_run/all.T The diff was not included because it is too large. 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