Simon Jakobi pushed to branch wip/sjakobi/T25450-march-native at Glasgow Haskell Compiler / GHC Commits: cfca4580 by Simon Jakobi at 2026-09-05T00:32:47+02:00 Implement -march=native for x86/x86_64 Add a -march=native flag that probes the host CPU and enables the matching CPU-feature DynFlags, so it affects both the NCG and the LLVM backend. Detected features are folded additively into the existing flags, so explicit -m... options are never disabled. The probe is a small C shim over GCC/Clang's __builtin_cpu_supports. The deviations that remain are documented in compiler/cbits/cpu_features_x86.c. The RTS exports the runtime symbols behind the builtin (__cpu_model & co.) so GHCi's runtime linker can load the ghc library where GHCi links statically, e.g. on Windows or musl. The flag is registered in expected-undocumented-flags.txt due to #27321. Thanks to @aratamizuki for pointing out the macOS AVX-512 XSAVE quirk and for testing! Closes #25450 Assisted-by: Claude Fable 5 - - - - - 17 changed files: - + changelog.d/march-native - changelog.d/print-enabled-cpu-features - + compiler/GHC/Driver/CpuFeatures.hs - compiler/GHC/Driver/DynFlags.hs - compiler/GHC/Driver/Session.hs - + compiler/cbits/cpu_features_x86.c - compiler/ghc.cabal.in - docs/users_guide/expected-undocumented-flags.txt - docs/users_guide/using.rst - rts/RtsSymbols.c - testsuite/tests/codeGen/should_gen_asm/all.T - + testsuite/tests/codeGen/should_gen_asm/march-native-enables-popcnt.asm - + testsuite/tests/codeGen/should_gen_asm/march-native-enables-popcnt.hs - testsuite/tests/driver/all.T - + testsuite/tests/driver/march_native.stdout - + testsuite/tests/driver/march_native_additive.stdout - + testsuite/tests/driver/march_native_unsupported_arch.stderr Changes: ===================================== changelog.d/march-native ===================================== @@ -0,0 +1,12 @@ +section: compiler +synopsis: Add -march=native flag +issues: #25450 +mrs: !16126 + +description: + GHC now supports ``-march=native`` on x86 and x86_64. It probes the CPU of the + machine running GHC and enables all of the corresponding ``-m...`` CPU-feature + options automatically (such as ``-msse4.2``, ``-mavx2``, ``-mbmi2`` and + ``-mfma``), for both the native code generator and the LLVM backend. The + detected features are enabled in addition to any explicitly requested feature + flags. The flag is rejected for non-x86 targets and when cross-compiling. ===================================== changelog.d/print-enabled-cpu-features ===================================== @@ -8,9 +8,11 @@ description: prints a JSON object describing the CPU features currently enabled for code generation, together with a set of ``-m...`` flags that reproduce the effective feature set for the current target. - Dynamic options such as ``-mavx2`` and ``-mbmi2`` are respected. :: + Dynamic options such as ``-mavx2`` and ``-mbmi2`` are respected, so the flag + can also be used to inspect which features :ghc-flag:`-march=native` detected + and enabled. :: - $ ghc -mavx2 --print-enabled-cpu-features + $ ghc -march=native --print-enabled-cpu-features {"tag":"enabled-cpu-features","version":1,"target":"x86_64-linux-gnu", - "features":["SSE","SSE2","SSE3","SSSE3","SSE4.1","SSE4.2","AVX","AVX2"], - "as_m_flags":["-mavx2"]} + "features":["SSE","SSE2","SSE3","SSSE3","SSE4.1","SSE4.2","AVX","AVX2","BMI1","BMI2","FMA"], + "as_m_flags":["-mavx2","-mbmi2","-mfma"]} ===================================== compiler/GHC/Driver/CpuFeatures.hs ===================================== @@ -0,0 +1,64 @@ +{-# LANGUAGE CPP #-} + +module GHC.Driver.CpuFeatures + ( X86CpuFeature(..) + , cachedX86CpuFeatures + ) where + +import GHC.Prelude + +import Data.Word (Word64) +import System.IO.Unsafe (unsafePerformIO) + +-- | x86 CPU features understood by GHC's native CPU feature probe. +data X86CpuFeature + = SSE2 + | SSE3 + | SSSE3 + | SSE4_1 + | SSE4_2 + | AVX + | AVX2 + | AVX512F + | AVX512BW + | AVX512CD + | AVX512DQ + | AVX512VL + | BMI1 + | BMI2 + | FMA + | GFNI + deriving (Eq, Ord, Show, Enum, Bounded) + +-- | Decode the bitmask returned by 'ghc_detect_x86_cpu_features'. +-- +-- Bit positions are constructor order, which must match the enum in +-- @compiler/cbits/cpu_features_x86.c@. +decodeX86CpuFeatureMask :: Word64 -> [X86CpuFeature] +decodeX86CpuFeatureMask mask = + [ feat + | feat <- [minBound .. maxBound] + , testBit mask (fromEnum feat) + ] + +-- | Low-level FFI access to the C probe. +detectX86CpuFeatureMask :: IO Word64 +#if defined(javascript_HOST_ARCH) +detectX86CpuFeatureMask = pure 0 +#else +detectX86CpuFeatureMask = c_ghc_detect_x86_cpu_features +#endif + +-- | Probe host x86 CPU features and decode them into an ordered feature list. +detectX86CpuFeatures :: IO [X86CpuFeature] +detectX86CpuFeatures = decodeX86CpuFeatureMask <$> detectX86CpuFeatureMask + +-- | The host's x86 CPU features, probed once and memoized. +cachedX86CpuFeatures :: [X86CpuFeature] +cachedX86CpuFeatures = unsafePerformIO detectX86CpuFeatures +{-# NOINLINE cachedX86CpuFeatures #-} + +#if !defined(javascript_HOST_ARCH) +foreign import ccall unsafe "ghc_detect_x86_cpu_features" + c_ghc_detect_x86_cpu_features :: IO Word64 +#endif ===================================== compiler/GHC/Driver/DynFlags.hs ===================================== @@ -473,6 +473,8 @@ data DynFlags = DynFlags { fma :: Bool, -- ^ Enable FMA instructions. gfni :: Bool, -- ^ Enable GFNI Instructions. la664 :: Bool, -- ^ Enable LA664 instructions + marchNative :: Bool, -- ^ @-march=native@ was requested; the host + -- CPU features are applied during flag parsing. -- Constants used to control the amount of optimization done. @@ -765,6 +767,7 @@ defaultDynFlags mySettings = gfni = False, -- For LoongArch, la464 is used by default. la664 = False, + marchNative = False, maxInlineAllocSize = 128, maxInlineMemcpyInsns = 32, ===================================== compiler/GHC/Driver/Session.hs ===================================== @@ -245,6 +245,8 @@ import GHC.Platform import GHC.Platform.Ways import GHC.Platform.Profile import GHC.Platform.ArchOS +import GHC.Platform.Host (hostPlatformArch) +import qualified GHC.Driver.CpuFeatures as Cpu import GHC.Unit.Types import GHC.Unit.Parser @@ -907,8 +909,10 @@ parseDynamicFlagsFull activeFlags cmdline logger dflags0 args = do unless (null errs) $ liftIO $ throwGhcExceptionIO $ errorsToGhcException $ map ((rdr . ppr . getLoc &&& unLoc) . errMsg) $ errs + dflags1' <- applyMarchNative dflags1 + -- check for disabled flags in safe haskell - let (dflags2, sh_warns) = safeFlagCheck cmdline dflags1 + let (dflags2, sh_warns) = safeFlagCheck cmdline dflags1' theWays = ways dflags2 unless (allowed_combination theWays) $ liftIO $ @@ -1743,6 +1747,7 @@ dynamic_flags_deps = [ , make_ord_flag defGhcFlag "mavx512vl" (noArg (\d -> d { avx512vl = True })) , make_ord_flag defGhcFlag "mfma" (noArg (\d -> d { fma = True })) , make_ord_flag defGhcFlag "mgfni" (noArg (\d -> d { gfni = True })) + , make_ord_flag defGhcFlag "march=native" (noArg (\d -> d { marchNative = True })) , make_ord_flag defGhcFlag "mla664" (noArg (\d -> d { la664 = True })) @@ -3826,6 +3831,53 @@ x86AsMFlags dflags = gfniFlags = [ "-mgfni" | gfni dflags ] +-- | Apply a requested @-march=native@ by probing the host CPU and enabling the +-- matching CPU-feature flags. +applyMarchNative :: MonadIO m => DynFlags -> m DynFlags +applyMarchNative dflags + | not (marchNative dflags) = return dflags + | otherwise = do + let arch = platformArch (targetPlatform dflags) + unless (arch == ArchX86 || arch == ArchX86_64) $ liftIO $ + throwGhcExceptionIO $ CmdLineError + "-march=native is only supported on x86 and x86_64 targets" + unless (arch == hostPlatformArch) $ liftIO $ + throwGhcExceptionIO $ CmdLineError + "-march=native is not supported when cross-compiling" + return (applyX86CpuFeatures Cpu.cachedX86CpuFeatures dflags) + +-- | Enable the 'DynFlags' CPU-feature fields corresponding to a probed set of +-- host x86 features. +applyX86CpuFeatures :: [Cpu.X86CpuFeature] -> DynFlags -> DynFlags +applyX86CpuFeatures feats dflags = dflags + { sseAvxVersion = foldr (max . Just) (sseAvxVersion dflags) sseLevels + , bmiVersion = foldr (max . Just) (bmiVersion dflags) bmiLevels + , avx512f = avx512f dflags || has Cpu.AVX512F + , avx512bw = avx512bw dflags || has Cpu.AVX512BW + , avx512cd = avx512cd dflags || has Cpu.AVX512CD + , avx512dq = avx512dq dflags || has Cpu.AVX512DQ + , avx512vl = avx512vl dflags || has Cpu.AVX512VL + , fma = fma dflags || has Cpu.FMA + , gfni = gfni dflags || has Cpu.GFNI + } + where + has feat = feat `elem` feats + sseLevels = [ lvl | feat <- feats, Just lvl <- [sseLevelOf feat] ] + bmiLevels = [ lvl | feat <- feats, Just lvl <- [bmiLevelOf feat] ] + sseLevelOf feat = case feat of + Cpu.SSE2 -> Just SSE2 + Cpu.SSE3 -> Just SSE3 + Cpu.SSSE3 -> Just SSSE3 + Cpu.SSE4_1 -> Just SSE4 + Cpu.SSE4_2 -> Just SSE42 + Cpu.AVX -> Just AVX1 + Cpu.AVX2 -> Just AVX2 + _ -> Nothing + bmiLevelOf feat = case feat of + Cpu.BMI1 -> Just BMI1 + Cpu.BMI2 -> Just BMI2 + _ -> Nothing + -- | Query if the target RTS has the given 'Ways'. It's computed from -- the @"RTS ways"@ field in the settings file. targetHasRTSWays :: DynFlags -> Ways -> Bool ===================================== compiler/cbits/cpu_features_x86.c ===================================== @@ -0,0 +1,97 @@ +#include <HsFFI.h> + +/* Runtime x86 CPU feature detection backing GHC.Driver.CpuFeatures + (-march=native). + + The bit positions in the returned mask are GHC's own; the enum below + must match the constructor order of X86CpuFeature in + GHC.Driver.CpuFeatures. + + The __builtin_cpu_* calls below compile to references to libgcc/compiler-rt + symbols (__cpu_model & co.), which GHCi's runtime linker can only resolve + because the RTS exports them: see RTS_X86_CPU_MODEL_SYMBOLS in + rts/RtsSymbols.c and keep its guards in sync with this file's. */ + +enum { + GHC_X86_FEAT_SSE2 = 0, + GHC_X86_FEAT_SSE3, + GHC_X86_FEAT_SSSE3, + GHC_X86_FEAT_SSE4_1, + GHC_X86_FEAT_SSE4_2, + GHC_X86_FEAT_AVX, + GHC_X86_FEAT_AVX2, + GHC_X86_FEAT_AVX512F, + GHC_X86_FEAT_AVX512BW, + GHC_X86_FEAT_AVX512CD, + GHC_X86_FEAT_AVX512DQ, + GHC_X86_FEAT_AVX512VL, + GHC_X86_FEAT_BMI1, + GHC_X86_FEAT_BMI2, + GHC_X86_FEAT_FMA, + GHC_X86_FEAT_GFNI +}; + +#if (defined(__i386__) || defined(__x86_64__)) \ + && (defined(__GNUC__) || defined(__clang__)) + +/* GFNI joined the __builtin_cpu_supports feature lists later than the + other features here (GCC 11; compiler-rt's cpu_model in LLVM 12). + Under an older bootstrap compiler we conservatively report no GFNI. */ +#if (defined(__clang_major__) && __clang_major__ >= 12) \ + || (!defined(__clang__) && defined(__GNUC__) && __GNUC__ >= 11) +#define GHC_HAS_CPU_SUPPORTS_GFNI 1 +#else +#define GHC_HAS_CPU_SUPPORTS_GFNI 0 +#endif + +HsWord64 ghc_detect_x86_cpu_features(void) +{ + __builtin_cpu_init(); + + HsWord64 feats = 0; + + /* __builtin_cpu_supports returns the feature's (nonzero) mask bit, + not 0/1, so it must be normalized before shifting. */ +#define GHC_CPU_FEATURE(name, bit) \ + if (__builtin_cpu_supports(name)) { feats |= ((HsWord64)1 << (bit)); } + + GHC_CPU_FEATURE("sse2", GHC_X86_FEAT_SSE2) + GHC_CPU_FEATURE("sse3", GHC_X86_FEAT_SSE3) + GHC_CPU_FEATURE("ssse3", GHC_X86_FEAT_SSSE3) + GHC_CPU_FEATURE("sse4.1", GHC_X86_FEAT_SSE4_1) + GHC_CPU_FEATURE("sse4.2", GHC_X86_FEAT_SSE4_2) + GHC_CPU_FEATURE("avx", GHC_X86_FEAT_AVX) + GHC_CPU_FEATURE("avx2", GHC_X86_FEAT_AVX2) + GHC_CPU_FEATURE("avx512f", GHC_X86_FEAT_AVX512F) + GHC_CPU_FEATURE("avx512bw", GHC_X86_FEAT_AVX512BW) + GHC_CPU_FEATURE("avx512cd", GHC_X86_FEAT_AVX512CD) + GHC_CPU_FEATURE("avx512dq", GHC_X86_FEAT_AVX512DQ) + GHC_CPU_FEATURE("avx512vl", GHC_X86_FEAT_AVX512VL) + GHC_CPU_FEATURE("bmi", GHC_X86_FEAT_BMI1) + GHC_CPU_FEATURE("bmi2", GHC_X86_FEAT_BMI2) + + /* FMA is usable only when the OS saves the AVX register state. However + compiler-rt's cpu_model/x86.c reports "fma" from the raw CPUID bit. */ + if (__builtin_cpu_supports("fma") && __builtin_cpu_supports("avx")) { + feats |= ((HsWord64)1 << GHC_X86_FEAT_FMA); + } + +#if GHC_HAS_CPU_SUPPORTS_GFNI + GHC_CPU_FEATURE("gfni", GHC_X86_FEAT_GFNI) +#endif + +#undef GHC_CPU_FEATURE + + return feats; +} + +#else + +/* Non-x86 host, or a compiler without __builtin_cpu_supports (e.g. MSVC): + report no features. */ +HsWord64 ghc_detect_x86_cpu_features(void) +{ + return 0; +} + +#endif ===================================== compiler/ghc.cabal.in ===================================== @@ -187,6 +187,7 @@ Library else c-sources: cbits/cutils.c + cbits/cpu_features_x86.c cbits/genSym.c cbits/keepCAFsForGHCi.c @@ -518,6 +519,7 @@ Library GHC.Driver.Config.StgToCmm GHC.Driver.Config.Tidy GHC.Driver.Config.StgToJS + GHC.Driver.CpuFeatures GHC.Driver.DynFlags GHC.Driver.IncludeSpecs GHC.Driver.Downsweep ===================================== docs/users_guide/expected-undocumented-flags.txt ===================================== @@ -74,6 +74,7 @@ -instantiated-with -keep-hi-file -keep-o-file +-march=native -n -no-keep-hi-file -no-keep-o-file ===================================== docs/users_guide/using.rst ===================================== @@ -539,7 +539,9 @@ The available mode flags are: Print a JSON object describing the CPU features currently enabled for code generation, together with a set of ``-m...`` flags that reproduce the effective feature set for the current target. - Dynamic options such as ``-mavx2`` and ``-mbmi2`` are respected. + Dynamic options such as ``-mavx2`` and ``-mbmi2`` are respected, so this flag + can also be used to inspect which features :ghc-flag:`-march=native` detected + and enabled. .. ghc-flag:: --print-debug-on :shortdesc: print whether GHC was built with ``-DDEBUG`` @@ -1897,6 +1899,34 @@ Some flags only make sense for particular target platforms. so this flag has no effect when used with the :ref:`native code generator <native-code-gen>` or the :ref:`LLVM backend <llvm-code-gen>`. +.. ghc-flag:: -march=native + :shortdesc: (x86 only) Enable all CPU features supported by the host + :type: dynamic + :category: platform-options + + (x86/x86_64 only) Probe the CPU of the machine running GHC and enable all of + the corresponding ``-m...`` CPU-feature options automatically (for example + ``-msse4.2``, ``-mavx2``, ``-mbmi2``, ``-mfma``). The detected features apply + to both the :ref:`native code generator <native-code-gen>` and the + :ref:`LLVM backend <llvm-code-gen>`. + + The detected features are enabled *in addition* to any CPU-feature flags you + pass explicitly, regardless of their order on the command line; ``-march=native`` + never disables a feature. + + The features that were detected and enabled can be inspected with + :ghc-flag:`--print-enabled-cpu-features`. + + .. warning:: + + Code compiled with ``-march=native`` may use instructions that are not + available on other CPUs, and is therefore not portable to a different + machine. + + Only x86 and x86_64 targets are supported so far; the flag is rejected on + other targets. It is also rejected when cross-compiling, since the host CPU + is then unrelated to the target. + Haddock ------- ===================================== rts/RtsSymbols.c ===================================== @@ -1039,6 +1039,30 @@ extern char **environ; #define RTS_ARM_OUTLINE_ATOMIC_SYMBOLS #endif +// libgcc/compiler-rt symbols behind __builtin_cpu_supports/__builtin_cpu_init, +// referenced by compiler/cbits/cpu_features_x86.c (-march=native). +// Without them the runtime linker cannot load the ghc library's object code +// (e.g. for plugins in a statically linked GHCi). Keep the guards in sync +// with cpu_features_x86.c. +#if (defined(i386_HOST_ARCH) || defined(x86_64_HOST_ARCH)) \ + && (defined(__GNUC__) || defined(__clang__)) +// __cpu_features2 holds the feature words beyond the first 32 (e.g. GFNI) +// and only exists in the runtimes of GCC >= 11 resp. LLVM >= 12. +#if (defined(__clang_major__) && __clang_major__ >= 12) \ + || (!defined(__clang__) && defined(__GNUC__) && __GNUC__ >= 11) +#define RTS_X86_CPU_FEATURES2_SYMBOLS \ + SymI_NeedsDataProto(__cpu_features2) +#else +#define RTS_X86_CPU_FEATURES2_SYMBOLS +#endif +#define RTS_X86_CPU_MODEL_SYMBOLS \ + SymI_NeedsProto(__cpu_indicator_init) \ + SymI_NeedsDataProto(__cpu_model) \ + RTS_X86_CPU_FEATURES2_SYMBOLS +#else +#define RTS_X86_CPU_MODEL_SYMBOLS +#endif + // Symbols defined by libc #define RTS_LIBC_SYMBOLS \ SymI_HasProto_redirect(atexit, atexit, STRENGTH_STRONG, SYM_TYPE_CODE) /* See Note [Strong symbols] */ \ @@ -1199,6 +1223,7 @@ RTS_OPENBSD_ONLY_SYMBOLS RTS_LIBC_SYMBOLS RTS_LIBGCC_SYMBOLS RTS_ARCH_LIBGCC_SYMBOLS +RTS_X86_CPU_MODEL_SYMBOLS RTS_FINI_ARRAY_SYMBOLS RTS_LIBFFI_SYMBOLS RTS_ARM_OUTLINE_ATOMIC_SYMBOLS @@ -1254,6 +1279,7 @@ void initLinkerRtsSyms (StrHashTable *symhash) { RTS_OPENBSD_ONLY_SYMBOLS RTS_LIBGCC_SYMBOLS RTS_ARCH_LIBGCC_SYMBOLS + RTS_X86_CPU_MODEL_SYMBOLS RTS_FINI_ARRAY_SYMBOLS RTS_LIBFFI_SYMBOLS RTS_ARM_OUTLINE_ATOMIC_SYMBOLS ===================================== testsuite/tests/codeGen/should_gen_asm/all.T ===================================== @@ -17,6 +17,11 @@ test('msse-option-order', [unless(arch('x86_64') or arch('i386'), skip), when(unregisterised(), skip)], compile_grep_asm, ['hs', False, '-msse4.2 -msse2']) test('mavx-should-enable-popcnt', [unless(arch('x86_64') or arch('i386'), skip), when(unregisterised(), skip)], compile_grep_asm, ['hs', False, '-mavx']) +# -march=native probes the host CPU, so gate on the host actually having SSE4.2 +# (have_cpu_feature reports nothing under cross, skipping the test there too). +test('march-native-enables-popcnt', + [unless((arch('x86_64') or arch('i386')) and have_cpu_feature('sse4_2'), skip), + when(unregisterised(), skip)], compile_grep_asm, ['hs', False, '-march=native']) test('avx512-int64-mul', [unless(arch('x86_64'), skip), when(unregisterised(), skip)], compile_grep_asm, ['hs', True, '-mavx512dq -mavx512vl']) test('avx512-int64-minmax', [unless(arch('x86_64'), skip), ===================================== testsuite/tests/codeGen/should_gen_asm/march-native-enables-popcnt.asm ===================================== @@ -0,0 +1 @@ +popcnt(?![0-9]) \ No newline at end of file ===================================== testsuite/tests/codeGen/should_gen_asm/march-native-enables-popcnt.hs ===================================== @@ -0,0 +1,11 @@ +-- `-march=native` enables the host's CPU features. On a host with SSE4.2 +-- (gated in all.T via have_cpu_feature) this makes popCount compile to a +-- `popcnt` instruction rather than the SSE2-baseline software fallback. +import Data.Bits + +{-# NOINLINE foo #-} +foo :: Int -> Int +foo x = 1 + popCount x + +main :: IO () +main = print (foo 42) ===================================== testsuite/tests/driver/all.T ===================================== @@ -7,6 +7,12 @@ def normalise_unknown_flag(msg): m = re.search(r'unrecognised flag: \S+', msg) return m.group(0) + '\n' if m else msg +def normalise_march_native_error(msg): + # Keep only the stable '-march=native ...' diagnostic; the program-name + # prefix and any usage trailer vary across configurations. + m = re.search(r'-march=native is [^\n]+', msg) + return m.group(0) + '\n' if m else msg + test('driver011', [extra_files(['A011.hs'])], makefile_test, ['test011']) test('driver012', [extra_files(['A012.hs'])], makefile_test, ['test012']) @@ -265,6 +271,29 @@ test('print_enabled_cpu_features_unknown_flag', run_command, ['{compiler} -mavx22 --print-enabled-cpu-features']) +# -march=native enables at least the x86_64 baseline (SSE2). The full feature +# set is host-dependent, so we only assert the always-present baseline. +test('march_native', + [unless(arch('x86_64') or arch('i386'), skip)], + run_command, + ['{compiler} -march=native --print-enabled-cpu-features | grep -o SSE2']) + +# On non-x86 targets -march=native must be rejected. +test('march_native_unsupported_arch', + [when(arch('x86_64') or arch('i386'), skip), + normalise_errmsg_fun(normalise_march_native_error), exit_code(1)], + run_command, + ['{compiler} -march=native --print-enabled-cpu-features']) + +# -march=native is additive with explicit -m flags, regardless of order: an +# explicitly requested feature (here AVX2, forced on independent of the host) is +# still present whether the flag comes before or after -march=native. +test('march_native_additive', + [unless(arch('x86_64') or arch('i386'), skip)], + run_command, + ['{compiler} -mavx2 -march=native --print-enabled-cpu-features | grep -o AVX2 && ' + '{compiler} -march=native -mavx2 --print-enabled-cpu-features | grep -o AVX2']) + test('T10219', normal, run_command, # `-x hspp` in make mode should work. # Note: need to specify `-x hspp` before the filename. ===================================== testsuite/tests/driver/march_native.stdout ===================================== @@ -0,0 +1 @@ +SSE2 ===================================== testsuite/tests/driver/march_native_additive.stdout ===================================== @@ -0,0 +1,2 @@ +AVX2 +AVX2 ===================================== testsuite/tests/driver/march_native_unsupported_arch.stderr ===================================== @@ -0,0 +1 @@ +-march=native is only supported on x86 and x86_64 targets View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/commit/cfca4580536b7bc4dd9713bec5278444... -- View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/commit/cfca4580536b7bc4dd9713bec5278444... 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