Sven Tennie pushed to branch wip/supersven/riscv-vectors at Glasgow Haskell Compiler / GHC Commits: dac9434c by Sven Tennie at 2025-06-29T12:13:42+02:00 Implement CPU vector support (RVV) detection for RISC-V - - - - - cfb7da61 by Sven Tennie at 2025-06-29T12:21:03+02:00 Introduce -mriscv-vlen driver argument with runtime check Ensure that the configured vlen fits to the detected one. - - - - - 134ffb9f by Sven Tennie at 2025-06-29T12:24:46+02:00 Compile AutoApply_V*.cmm and Jumps_V*.cmm with vector support If the running CPU does not support RVV, this code will not be executed. However, at build time, we have to emit (prepare) it. - - - - - d56e98f5 by Sven Tennie at 2025-06-29T12:28:10+02:00 Emit code for RVV This includes adding the vector registers to the register allocator and adding support for the related MachOps to the cod generator. - - - - - 5d2c3b26 by Sven Tennie at 2025-06-29T12:31:32+02:00 Detect RVV CPU features and make them configurable for CROSS_EMULATOR Unfortunately, the cpuinfo Python package is abandonned. Thus, we just add RVV detection here (and not upstream.) cpuinfo is not executed on the CROSS_EMULATOR. So, we make supported features configurable. - - - - - d7a7aa64 by Sven Tennie at 2025-06-29T12:33:52+02:00 Adjust SIMD test to support/use RISC-V - - - - - b6ea3f6a by Sven Tennie at 2025-06-29T12:34:24+02:00 WIP: Test for the RVV c calling convention - - - - - 37 changed files: - compiler/CodeGen.Platform.h - compiler/GHC/Cmm/CallConv.hs - compiler/GHC/CmmToAsm/Config.hs - compiler/GHC/CmmToAsm/Format.hs - compiler/GHC/CmmToAsm/RV64.hs - compiler/GHC/CmmToAsm/RV64/CodeGen.hs - compiler/GHC/CmmToAsm/RV64/Instr.hs - compiler/GHC/CmmToAsm/RV64/Ppr.hs - compiler/GHC/CmmToAsm/RV64/Regs.hs - compiler/GHC/CmmToAsm/Reg/Graph/TrivColorable.hs - compiler/GHC/CmmToAsm/Reg/Linear.hs - compiler/GHC/CmmToAsm/Reg/Linear/RV64.hs - compiler/GHC/Driver/Config/CmmToAsm.hs - compiler/GHC/Driver/Config/StgToCmm.hs - compiler/GHC/Driver/DynFlags.hs - compiler/GHC/Driver/Session.hs - compiler/GHC/Linker/ExtraObj.hs - compiler/GHC/Platform/Reg/Class.hs - compiler/GHC/StgToCmm/Config.hs - compiler/GHC/StgToCmm/Prim.hs - compiler/GHC/Utils/Outputable.hs - docs/users_guide/using.rst - hadrian/src/Settings/Packages.hs - libraries/unix - rts/CheckVectorSupport.c - rts/RtsStartup.c - rts/include/stg/MachRegs.h - rts/include/stg/MachRegs/riscv64.h - testsuite/driver/cpu_features.py - testsuite/driver/cpuinfo.py - testsuite/driver/testglobals.py - testsuite/driver/testlib.py - + testsuite/tests/simd/should_run/VectorCCallConv.hs - + testsuite/tests/simd/should_run/VectorCCallConv.stdout - + testsuite/tests/simd/should_run/VectorCCallConv_c.c - testsuite/tests/simd/should_run/all.T - testsuite/tests/simd/should_run/simd013C.c The diff was not included because it is too large. View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/compare/463de8893208cdc5a49a42b5de99517... -- View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/compare/463de8893208cdc5a49a42b5de99517... You're receiving this email because of your account on gitlab.haskell.org.