Re: Inquiry about Supporting RISC-V 32 in Haskell

Hi Shiwei,

Let me try to draw up a more visual representation do the current pipelines over the weekend. That might also explain why I think the subset might work as the intermediate steps *do* carry register width.

Cheers, Moritz

On Thu, 8 Jun 2023 at 2:44 PM, 卢诗炜 wrote:

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Moritz,

Thank you for your detailed response. However, we think that RV32 is not a subset of RV64, and that the instruction selection logic for RV32 and RV64 may differ. Because RV32 and RV64 have different register widths, it is sometimes necessary to use different instructions than RV64 to ensure correct results.

We plan to support RV32 in Native Code Generation. And we may draw inspiration from your support for RV64. We do want to be able to support RV32I+MAF, also include C extensions.

Do you have any comments or suggestions?

For what it's worth, I generally agree with MOritz that it should be

Moritz Angermann writes: possible for one RISC-V NCG backend to handle both RV32 and RV64. While it's true that RV32 may not be a strict subset of RV64, it is similar enough that it should be possible to work. For instance, the same approach is used within GHC to handle x86-64 and i386; in that case the NCG implementation is quite maintainable despite the rather considerable differences between the two ISAs. Cheers, - Ben