Hey All, Is there any reasons *not* to add SSE / AVX register support to the llvm 32 bit x86 ghc calling convention? It looks like (as with x86_64)
We would like code compiled with the LLVM back-end that doesn't use SIMD vectors to inter-operate with code compiled with the native codegen. The native codegen passes floating point arguments on the stack, so if we changed the GHC LLVM calling convention to pass Floats and Doubles in registers, we would need to change the native codegen to do the same. Or are you suggesting that we only pass SIMD short-vectors in the xmm registers on x86? I changed the calling convention (for both back-ends) when I did the SIMD work. It was a lucky accident that I didn't have to patch LLVM. Geoff On 07/08/2013 07:57 PM, Carter Schonwald wrote: that adding additional simd registers to the calling convention would be fully backwards compatible with current ghc approach to 32bit function calls, but would allow ghc 32bit (at some future point) to have decent floating point performance when applicable.
I'm ok either way, but would be helpful to get some opinions.
just to recap, i'm working on getting a patch sorted out for adding
AVX support to the ghc x86_64 LLVM calling convention http://ghc.haskell.org/trac/ghc/ticket/8033, and now would be a good time to add anything to the 32bit x86 calling convention
thanks -Carter