#12469: Memory fence on writes to MutVar/Array missing on ARM -------------------------------------+------------------------------------- Reporter: rrnewton | Owner: Type: bug | Status: patch Priority: normal | Milestone: 8.0.2 Component: Compiler | Version: 8.0.1 Resolution: | Keywords: memory model Operating System: Unknown/Multiple | Architecture: Type of failure: Incorrect result | Unknown/Multiple at runtime | Test Case: Blocked By: | Blocking: 12537 Related Tickets: | Differential Rev(s): Phab:D2495 Wiki Page: | Phab:D2525 -------------------------------------+------------------------------------- Comment (by trommler): Replying to [comment:23 trommler]:
Replying to [comment:22 erikd]:
@trommler Yes, that may well be worth while. OK, I am working on it and will report back. So, I compiled all of Stackage 7.x on a POWER 8 LPAR instance with 8 CPUs, so no qemu involved and saw five packages fail with a panic in `mkFastStringWith`. A few more failed with segfaults in `Setup build -j8`.
I used ghc 8.0.1 patched with the two patches in this ticket. My theory is that `lwsync` is not a strong enough barrier for a write barrier. So far I thought a write barrier is the same as a store-store barrier and hence `lwsync` is the right choice on PowerPC. I could put a `sync` and see what happens but I would like to know what I am doing when using that big a hammer. So what is the semantics of a write barrier with respect to other processors/cores? -- Ticket URL: http://ghc.haskell.org/trac/ghc/ticket/12469#comment:24 GHC http://www.haskell.org/ghc/ The Glasgow Haskell Compiler