Re: [GHC] #10375: arm: ghci hits an illegal instruction

5 Sep 2015

      #10375: arm: ghci hits an illegal instruction
-------------------------------------+---------------------------------
        Reporter:  erikd             |                   Owner:
            Type:  bug               |                  Status:  new
        Priority:  high              |               Milestone:  7.10.3
       Component:  GHCi              |                 Version:  7.10.1
      Resolution:                    |                Keywords:
Operating System:  Unknown/Multiple  |            Architecture:  arm
 Type of failure:  GHCi crash        |               Test Case:
      Blocked By:                    |                Blocking:
 Related Tickets:                    |  Differential Revisions:
-------------------------------------+---------------------------------

Comment (by erikd):

 If I configure the build with `--enable-unregistered`, built it and then
 re-ran my tests.

 The program still crashes with SIGILL, but I now get a sensible backtrace:

 {{{
 GHCi, version 7.11.20150905: http://www.haskell.org/ghc/  :? for help

 Program received signal SIGILL, Illegal instruction.
 0x03ff9dbc in stg_ap_v_fast ()
 (gdb) bt
 #0  0x03ff9dbc in stg_ap_v_fast ()
 #1  0x03fc6ce6 in StgRun (f=0x3ff9db4 , basereg=0x49d2090
 ) at
     rts/StgCRun.c:81
 #2  0x03fca52a in schedule (initialCapability=0x49d2080 <MainCapability>,
 task=0x49e62c0) at
     rts/Schedule.c:524
 #3  0x03fcc5e6 in scheduleWaitThread (tso=0xb6c07000, ret=0x0,
 pcap=0xbeffeb74) at
     rts/Schedule.c:2429
 #4  0x03fbc7e4 in rts_evalLazyIO (cap=0xbeffeb74, p=0x402d470
 , ret=0x0) at
     rts/RtsAPI.c:500
 #5  0x03fce2be in hs_main (argc=3, argv=0xbeffed64, main_closure=0x402d470
 ,
     rts_config=...) at rts/RtsMain.c:64
 #6  0x00141508 in main ()
 }}}

 and if I disassemble at the SIGILL I get:

 {{{
 (gdb) disassemble
 Dump of assembler code for function stg_ap_v_fast:
    0x03ff9db4 <+0>:     push    {r7, lr}
    0x03ff9db6 <+2>:     sub     sp, #32
    0x03ff9db8 <+4>:     add     r7, sp, #0
    0x03ff9dba <+6>:     ldr     r3, [pc, #508]  ; (0x3ff9fb8
 )
 => 0x03ff9dbc <+8>:     ldr     r3, [r3, #0]
    0x03ff9dbe <+10>:    and.w   r3, r3, #3
 }}}

 Now to figure out why that load instruction is illegal.

--
Ticket URL: http://ghc.haskell.org/trac/ghc/ticket/10375#comment:40
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