#12469: Memory fence on writeIORef missing on ARM -------------------------------------+------------------------------------- Reporter: rrnewton | Owner: Type: bug | Status: patch Priority: normal | Milestone: 8.2.1 Component: Compiler | Version: 8.0.1 Resolution: | Keywords: memory model Operating System: Unknown/Multiple | Architecture: | Unknown/Multiple Type of failure: None/Unknown | Test Case: Blocked By: | Blocking: Related Tickets: | Differential Rev(s): Phab:D2495 Wiki Page: | -------------------------------------+------------------------------------- Comment (by rrnewton): That looks like the right kind of thing, but it needs to be conditional -- only on the ARM backend. We wouldn't want to slow down x86. Ideally, it would only apply in `-threaded` mode to boot, but my current understanding is that we only make the distinction at the final link phase (which runtime to link), not as a different "way" during compilation. -- Ticket URL: http://ghc.haskell.org/trac/ghc/ticket/12469#comment:7 GHC http://www.haskell.org/ghc/ The Glasgow Haskell Compiler