#10375: arm: ghci hits an illegal instruction
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Reporter: erikd | Owner:
Type: bug | Status: new
Priority: normal | Milestone: 7.10.2
Component: GHCi | Version: 7.10.1
Resolution: | Keywords:
Operating System: Unknown/Multiple | Architecture: arm
Type of failure: GHCi crash | Test Case:
Blocked By: | Blocking:
Related Tickets: | Differential Revisions:
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Comment (by erikd):
Added a `static int count=0` variable that gets incremented each time the
`schedule` function passes through the `ThreadRunGHC` case statement. I
then added a printf:
{{{
printf ("%d : %u %u\n", count, cap->no, (unsigned)cap->r.rCurrentTSO->id);
}}}
and running it with the `getChar` in `.ghci` I note that the last set of
values printed by this statement before it segfaults is:
{{{
183 : 0 22
}}}
So I run it again and attached GDB when the process is waiting for
`getChar` and then set a breakpoint:
{{{
(gdb) break rts/Schedule.c:490 if (count == 183 && cap->no == 0 &&
cap->r.rCurrentTSO->id == 22)
}}}
only to have the process crash in a completely different way:
{{{
Program received signal SIGILL, Illegal instruction.
0xb2c56c7a in schedule (initialCapability=0xb2c96180 <MainCapability>,
task=0x10faf8) at rts/Schedule.c:491
(gdb) bt
#0 0xb2c56c7a in schedule (initialCapability=0xb2c96180 <MainCapability>,
task=0x10faf8) at rts/Schedule.c:491
#1 0xb2c59040 in scheduleWaitThread (tso=0xb2707000, ret=0x0,
pcap=0xbeffe944)
at rts/Schedule.c:2408
#2 0xb2c47c98 in rts_evalLazyIO (cap=0xbeffe944, p=0xd2c30