#8033: add AVX register support to llvm calling convention -------------------------------------+------------------------------------ Reporter: carter | Owner: carter Type: task | Status: new Priority: normal | Milestone: Component: Compiler | Version: 7.7 Resolution: | Keywords: Operating System: Unknown/Multiple | Architecture: Unknown/Multiple Type of failure: None/Unknown | Difficulty: Unknown Test Case: | Blocked By: Blocking: | Related Tickets: -------------------------------------+------------------------------------ Comment (by carter): {{{ // Pass in STG registers for 128bit simd vectors CCIfType<[ v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCIfSubtarget<"hasSSE1()", CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>, // Pass in STG registers for first 6 256bit simd vectors CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCIfSubtarget<"hasAVX()", CCAssignToReg<[ YMM1, YMM2, YMM3, YMM4, YMM5, YMM6]>>> }}} I propose adding this to the x86_32 convention as per @gmainland's suggestion on list. Please indicate on this ticket if that modification is ok :) -- Ticket URL: http://ghc.haskell.org/trac/ghc/ticket/8033#comment:13 GHC http://www.haskell.org/ghc/ The Glasgow Haskell Compiler