#10375: arm: ghci hits an illegal instruction -------------------------------------+------------------------------------- Reporter: erikd | Owner: Type: bug | Status: new Priority: high | Milestone: 7.10.3 Component: Runtime System | Version: 7.10.1 (Linker) | Resolution: | Keywords: Operating System: Unknown/Multiple | Architecture: arm Type of failure: GHCi crash | Test Case: Blocked By: | Blocking: Related Tickets: | Differential Revisions: -------------------------------------+------------------------------------- Comment (by rwbarton): Replying to [comment:41 erikd]:
From: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0489c/CIHGJHE...
The instruction matches:
{{{ op{type}{cond} Rt, [Rn, #offset]! ; pre-indexed }}}
but the under the section titled "Register restrictions" it says:
{{{ Rn must be different from Rt in the pre-index and post-index forms. }}}
Pre-indexed instructions have a trailing `!`, though. This syntax means something like "increment `Rn` by `#offset`, then operate on the value pointed to by the updated `Rn`". That's why `Rn` cannot also appear as `Rt`, there would be two stores to the same register in the same instruction. The offending instruction here is `ldr r3, [r3, #0]` without a `!`, which is just a `r3 = *r3`. I suspect the issue is actually executing Thumb code in ARM mode, as appears to be the case in #10863, though I still have no idea as to the cause. -- Ticket URL: http://ghc.haskell.org/trac/ghc/ticket/10375#comment:47 GHC http://www.haskell.org/ghc/ The Glasgow Haskell Compiler