#15983: Built-in support for half-floats -------------------------------------+------------------------------------- Reporter: lerkok | Owner: (none) Type: feature request | Status: new Priority: normal | Milestone: 8.6.3 Component: Compiler | Version: 8.6.2 Resolution: | Keywords: Operating System: Unknown/Multiple | Architecture: | Unknown/Multiple Type of failure: None/Unknown | Test Case: Blocked By: | Blocking: Related Tickets: | Differential Rev(s): Wiki Page: | -------------------------------------+------------------------------------- Comment (by carter): I don’t think ghc can support half float any time soon as a built in. 1) for cpu native workloads there’s not a big win afik... because the value in gpu programming is from the bandwidth saving. Aka it’s more of a compact serialization than a representationfor computing. 2) while there is some new hardware with half float or even one bit float suport, those are all seemingly deep learning dedicated hardware. 3) abi concerns - we barely even touch the surface area for handling simd computations with float or double. That stuff needs to be a lot more mature before touching half float. Cause scalar half float isn’t useful from a performance perspective. All in all, the intent is good. But I’d be inclined to Mark this as a won’t fix until ghc simd becomes a lot more mature and commodity hardware has really wide spread support. Which will be years from now at the soonest -- Ticket URL: http://ghc.haskell.org/trac/ghc/ticket/15983#comment:1 GHC http://www.haskell.org/ghc/ The Glasgow Haskell Compiler