#8033: add AVX register support to llvm calling convention -------------------------------------+------------------------------------ Reporter: carter | Owner: carter Type: task | Status: new Priority: normal | Milestone: Component: Compiler | Version: 7.7 Resolution: | Keywords: Operating System: Unknown/Multiple | Architecture: Unknown/Multiple Type of failure: None/Unknown | Difficulty: Unknown Test Case: | Blocked By: Blocking: | Related Tickets: -------------------------------------+------------------------------------ Comment (by gmainland): SSE2 instructions are always available on the 64-bit Intel architecture. -- Ticket URL: http://ghc.haskell.org/trac/ghc/ticket/8033#comment:25 GHC http://www.haskell.org/ghc/ The Glasgow Haskell Compiler