[GHC] #13852: Can we have more SIMD primops, corresponding to the untapped AVX etc. instructions?
#13852: Can we have more SIMD primops, corresponding to the untapped AVX etc. instructions? -------------------------------------+------------------------------------- Reporter: | Owner: (none) leftaroundabout | Type: feature | Status: new request | Priority: normal | Milestone: Component: Compiler | Version: 8.0.1 (LLVM) | Keywords: | Operating System: Unknown/Multiple Architecture: x86_64 | Type of failure: None/Unknown (amd64) | Test Case: | Blocked By: Blocking: | Related Tickets: Differential Rev(s): | Wiki Page: -------------------------------------+------------------------------------- [http://hackage.haskell.org/package/ghc-prim-0.5.0.0/docs/GHC- Prim.html#g:28 GHC.Prim] contains a good couple of vectorised instructions, which can be [http://hackage.haskell.org/package/primitive- simd-0.1.0.0/docs/Data-Primitive-SIMD.html used by libraries] for generating nice fast e.g. sums of floating-point vectors. However, several instructions that modern processors could vectorise are missing there. In particular, I would like to be able to use the VPSLLVD...VPSRAVD shifting operations, and at some point perhaps VPMAXSQ...VPMINUQ maximum/minimum operations. It would be great if corresponding primops could be added. Else I would like to know – where is this stuff even defined? [http://hackage.haskell.org/package/ghc- prim-0.5.0.0/docs/src/GHC.Prim.html GHC.Prim] as such seems to be merely an automatically-generated dummy module, mostly for Haddock. (On the other hand, I find it also a bit strange that there are primops for [http://hackage.haskell.org/package/ghc-prim-0.5.0.0/docs/GHC- Prim.html#v:quotInt8X16-35- integer division], which is apparently [https://stackoverflow.com/questions/16822757/sse-integer-division not supported by SSE/AVX] at all!) -- Ticket URL: http://ghc.haskell.org/trac/ghc/ticket/13852 GHC http://www.haskell.org/ghc/ The Glasgow Haskell Compiler
#13852: Can we have more SIMD primops, corresponding to the untapped AVX etc. instructions? -------------------------------------+------------------------------------- Reporter: leftaroundabout | Owner: (none) Type: feature request | Status: new Priority: normal | Milestone: Component: Compiler (LLVM) | Version: 8.0.1 Resolution: | Keywords: Operating System: Unknown/Multiple | Architecture: x86_64 | (amd64) Type of failure: None/Unknown | Test Case: Blocked By: | Blocking: Related Tickets: | Differential Rev(s): Wiki Page: | -------------------------------------+------------------------------------- Comment (by simonpj): Mayte [wiki:AddingNewPrimitiveOperations] may help? -- Ticket URL: http://ghc.haskell.org/trac/ghc/ticket/13852#comment:1 GHC http://www.haskell.org/ghc/ The Glasgow Haskell Compiler
#13852: Can we have more SIMD primops, corresponding to the untapped AVX etc. instructions? -------------------------------------+------------------------------------- Reporter: leftaroundabout | Owner: (none) Type: feature request | Status: new Priority: normal | Milestone: Component: Compiler (LLVM) | Version: 8.0.1 Resolution: | Keywords: Operating System: Unknown/Multiple | Architecture: x86_64 | (amd64) Type of failure: None/Unknown | Test Case: Blocked By: | Blocking: Related Tickets: | Differential Rev(s): Wiki Page: | -------------------------------------+------------------------------------- Comment (by leftaroundabout): That definitely helps, but I'm still far from understanding what I'd need to do do enable those AVX operations myself. [https://ghc.haskell.org/trac/ghc/wiki/AddingNewPrimitiveOperations The linked Wiki article] doesn't seem to be quite up-to-date WRT [https://github.com/ghc/ghc/blob/master/rts/PrimOps.cmm Primops.cmm], in which I can neither find any hint of any of the vectorised instructions, nor the {{{quotIntegerzh}}} example. -- Ticket URL: http://ghc.haskell.org/trac/ghc/ticket/13852#comment:2 GHC http://www.haskell.org/ghc/ The Glasgow Haskell Compiler
#13852: Can we have more SIMD primops, corresponding to the untapped AVX etc. instructions? -------------------------------------+------------------------------------- Reporter: leftaroundabout | Owner: (none) Type: feature request | Status: new Priority: normal | Milestone: Component: Compiler (LLVM) | Version: 8.0.1 Resolution: | Keywords: Operating System: Unknown/Multiple | Architecture: x86_64 | (amd64) Type of failure: None/Unknown | Test Case: Blocked By: | Blocking: Related Tickets: | Differential Rev(s): Wiki Page: | -------------------------------------+------------------------------------- Comment (by hsyl20): Primitive operations on vectors are named `Vec*` in [https://github.com/ghc/ghc/blob/b1fa386cdae1af45fdd3519014be850f83414ab3/com... prelude/primops.txt.pp] (e.g, `VecDivOp`). The genprimopcode utility generates a primop per vector type and width. For instance in compiler/stage1/build/primop-list.hs-incl: {{{ , (VecDivOp FloatVec 4 W32) , (VecDivOp FloatVec 2 W64) , (VecDivOp FloatVec 8 W32) , (VecDivOp FloatVec 4 W64) , (VecDivOp FloatVec 16 W32) , (VecDivOp FloatVec 8 W64) }}} These are converted from Stg to Cmm by `translateOp` in [https://github.com/ghc/ghc/blob/b1fa386cdae1af45fdd3519014be850f83414ab3/com... codeGen/StgCmmPrim.hs]. For instance, `VecDivOp FloatVec` becomes `MO_VF_Quot`. Then you need to use the LLVM backend to convert Cmm into LLVM (textual) IR. This is done by `genMachOp_slow` in [https://github.com/ghc/ghc/blob/b1fa386cdae1af45fdd3519014be850f83414ab3/com... llvmGen/LlvmCodeGen/CodeGen.hs]. Finally LLVM generates the assembly and GHC [https://github.com/ghc/ghc/blob/b1fa386cdae1af45fdd3519014be850f83414ab3/com... replaces some instructions] because it can't guarantee that the alignment is correct. Note that the native code generator don't support them yet: you have to use the LLVM backend. If the instructions you want are supported by LLVM, they should be relatively easy to add. -- Ticket URL: http://ghc.haskell.org/trac/ghc/ticket/13852#comment:3 GHC http://www.haskell.org/ghc/ The Glasgow Haskell Compiler
#13852: Can we have more SIMD primops, corresponding to the untapped AVX etc. instructions? -------------------------------------+------------------------------------- Reporter: leftaroundabout | Owner: (none) Type: feature request | Status: new Priority: normal | Milestone: Component: Compiler (LLVM) | Version: 8.0.1 Resolution: | Keywords: SIMD Operating System: Unknown/Multiple | Architecture: x86_64 | (amd64) Type of failure: None/Unknown | Test Case: Blocked By: | Blocking: Related Tickets: | Differential Rev(s): Wiki Page: | -------------------------------------+------------------------------------- Changes (by bgamari): * keywords: => SIMD -- Ticket URL: http://ghc.haskell.org/trac/ghc/ticket/13852#comment:4 GHC http://www.haskell.org/ghc/ The Glasgow Haskell Compiler
#13852: Can we have more SIMD primops, corresponding to the untapped AVX etc. instructions? -------------------------------------+------------------------------------- Reporter: leftaroundabout | Owner: (none) Type: feature request | Status: new Priority: normal | Milestone: Component: Compiler (LLVM) | Version: 8.0.1 Resolution: | Keywords: SIMD Operating System: Unknown/Multiple | Architecture: x86_64 | (amd64) Type of failure: None/Unknown | Test Case: Blocked By: | Blocking: Related Tickets: | Differential Rev(s): Wiki Page: | -------------------------------------+------------------------------------- Comment (by dominic): This looks like it would be a good GSoC project to me. What do others think? -- Ticket URL: http://ghc.haskell.org/trac/ghc/ticket/13852#comment:5 GHC http://www.haskell.org/ghc/ The Glasgow Haskell Compiler
#13852: Can we have more SIMD primops, corresponding to the untapped AVX etc. instructions? -------------------------------------+------------------------------------- Reporter: leftaroundabout | Owner: (none) Type: feature request | Status: new Priority: normal | Milestone: Component: Compiler (LLVM) | Version: 8.0.1 Resolution: | Keywords: SIMD Operating System: Unknown/Multiple | Architecture: x86_64 | (amd64) Type of failure: None/Unknown | Test Case: Blocked By: | Blocking: Related Tickets: | Differential Rev(s): Wiki Page: | -------------------------------------+------------------------------------- Comment (by bgamari): While technically the ptoject is of the right scale for a GSoC student, I'm a bit weary of suggesting it as a relatively small fraction of the community would stand to benefit from its completion. -- Ticket URL: http://ghc.haskell.org/trac/ghc/ticket/13852#comment:6 GHC http://www.haskell.org/ghc/ The Glasgow Haskell Compiler
#13852: Can we have more SIMD primops, corresponding to the untapped AVX etc. instructions? -------------------------------------+------------------------------------- Reporter: leftaroundabout | Owner: (none) Type: feature request | Status: new Priority: normal | Milestone: Component: Compiler (LLVM) | Version: 8.0.1 Resolution: | Keywords: SIMD Operating System: Unknown/Multiple | Architecture: x86_64 | (amd64) Type of failure: None/Unknown | Test Case: Blocked By: | Blocking: Related Tickets: | Differential Rev(s): Wiki Page: | -------------------------------------+------------------------------------- Comment (by dominic): Maybe there are other bits of the code generator which would give more bang for buck? I think I will propose this anyway but with a comment to ask the GSoC student to spend a few days seeing if this is the highest priority (but doable) part of the CG that needs addressing. -- Ticket URL: http://ghc.haskell.org/trac/ghc/ticket/13852#comment:7 GHC http://www.haskell.org/ghc/ The Glasgow Haskell Compiler
participants (1)
-
GHC