#8033: add AVX register support to llvm calling convention -------------------------------------+------------------------------------ Reporter: carter | Owner: carter Type: task | Status: new Priority: normal | Milestone: Component: Compiler | Version: 7.7 Resolution: | Keywords: Operating System: Unknown/Multiple | Architecture: Unknown/Multiple Type of failure: None/Unknown | Difficulty: Unknown Test Case: | Blocked By: Blocking: | Related Tickets: -------------------------------------+------------------------------------ Comment (by gmainland): I support a patch for x86_64 that passes 256-bit vectors in YMM registers when AVX is available. I am ambivalent about changing the x86_32 calling conventions, but it seems to me it would be a mistake to continue passing Float and Double arguments on the stack when SSE2 instructions are available. -- Ticket URL: http://ghc.haskell.org/trac/ghc/ticket/8033#comment:27 GHC http://www.haskell.org/ghc/ The Glasgow Haskell Compiler