#8033: add AVX register support to llvm calling convention -------------------------------------+------------------------------------ Reporter: carter | Owner: carter Type: task | Status: new Priority: normal | Milestone: Component: Compiler | Version: 7.7 Resolution: | Keywords: Operating System: Unknown/Multiple | Architecture: Unknown/Multiple Type of failure: None/Unknown | Difficulty: Unknown Test Case: | Blocked By: Blocking: | Related Tickets: -------------------------------------+------------------------------------ Comment (by carter): Ok, so we should change the hasSSE1 to hasSSE2 to simplify adding short vector / simd support uniformly when its available (ie, for now NOT have 32bit ghc put floats and doubles in registers, thats something we can consider at some future point perhaps). So for now (a) {{{ // Pass in STG registers for floats, doubles and 128bit simd vectors CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>, // Pass in STG registers for 256bit simd vectors CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCIfSubtarget<"hasAVX()", CCAssignToReg<[ YMM1, YMM2, YMM3, YMM4, YMM5, YMM6]>>> }}} for x86_64 and {{{ // Pass in STG registers for floats, doubles and 128bit simd vectors CCIfType<[ v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>, // Pass in STG registers for 256bit simd vectors CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCIfSubtarget<"hasAVX()", CCAssignToReg<[ YMM1, YMM2, YMM3, YMM4, YMM5, YMM6]>>> }}} for x86_32? (though we could use the same stanza ) or (b) {{{ // Pass in STG registers for floats, doubles and 128bit simd vectors CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>, // Pass in STG registers for 256bit simd vectors CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCIfSubtarget<"hasAVX()", CCAssignToReg<[ YMM1, YMM2, YMM3, YMM4, YMM5, YMM6]>>> }}} for BOTH? (but not use the registers for floats and doubles in x86_32 for now) either change will be compatible with past and current GHCs -- Ticket URL: http://ghc.haskell.org/trac/ghc/ticket/8033#comment:26 GHC http://www.haskell.org/ghc/ The Glasgow Haskell Compiler