Many attempts were done in this area in the late 80s/early 90s (and before if you don't focus on lazy evaluation; search lisp machine). Search hardware graph reduction. The major problem has always been that producing a dedicated CPU is expensive and there's no way to keep up with the progresses in general purpose processor that can justify investments with a hugely larger user base. At some point there were even attempts of placing computation in the memory itself (typically using very fine grain combinators, SKI reduction and the such) People have given up even on hardware support for small subproblems, such as garbage collection. As for modifying the instruction set of an Intel processor, I don't know how feasible it is. But even if it is, consider that the entire architecture, pipelining, caching, predictions, speculative everythinbg etc. is hugely optimized for the typical workflow. You change that and all bets are off w.r.t performance and you may or not be ahead of the same CPU executing normal code out of a haskell compiler. On Tue, Jan 19, 2016 at 5:12 PM, Henning Thielemann < lemming@henning-thielemann.de> wrote:
Hi all,
every now and then I think it would be cool to have a microprocessor that supports Haskell in a way. A processor where lazy evaluation is not overhead but an optimization opportunity, a processor that can make use of the explicit data dependencies in Haskell programs in order to utilize many computation units in parallel. I know of the Reduceron project, which evolves only slowly and if it somewhen is ready for use it is uncertain whether it can compete with stock CPUs since FPGA's need much more chip space for the same logic.
I got to know that in todays x86 processors you can alter the instruction set, which is mainly used for bugfixes. Wouldn't it be interesting to add some instructions for Haskell support? However, I suspect that such a patch might be rendered invalid by new processor generations with changed internal details. Fortunately, there are processors that are designed for custom instruction set extensions: https://en.wikipedia.org/wiki/Xtensa
Would it be sensible to create a processor based on such a design? I have no idea what it might cost, and you would still need some peripheral circuitry to run it. What could processor instructions for Haskell support look like? Has anyone already thought in this direction? _______________________________________________ Haskell-Cafe mailing list Haskell-Cafe@haskell.org http://mail.haskell.org/cgi-bin/mailman/listinfo/haskell-cafe