Kind of tangential, but bluespev verilog is a "Haskell inspired" version of
verilog that has a strong Haskell flavour (typeclasses, purity, a
rudimentary effect system that tracks combinational versus state based
logic, clock domains embedded into the type, width polymorphic functions,
etc).
It's a really great way to see what a haskell-like-hardware description
language could look like :)
Cheers
siddharth
On Sun 21 Oct, 2018, 12:34 Joachim Durchholz,
Am 21.10.18 um 04:52 schrieb Will Yager:
This is the basis of projects like Clash (Haskell to HDLs). I imagine
one could extend the clash approach to generate allocation-free assembly from the same (large) subset of Haskell.
Is that subset described somewhere?
Regards, Jo _______________________________________________ Haskell-Cafe mailing list To (un)subscribe, modify options or view archives go to: http://mail.haskell.org/cgi-bin/mailman/listinfo/haskell-cafe Only members subscribed via the mailman list are allowed to post.
-- Sending this from my phone, please excuse any typos!