ANN: clash-0.1.3.0 (Functional Hardware Descriptions)
Hello, I am pleased to announce an incremental update to CLaSH, version 0.1.3.0. CLaSH can translate a (semantic) subset of Haskell to RTL-style VHDL. Instead of being an embedded DSL like Lava or ForSyDe, CLaSH takes are more 'traditional' approach to synthesis/compilation. It uses the GHC API as a front-end for parsing, type-checking and desugaring the Haskell source. It then exhaustively applies a list of meaning-preserving transformations to the intermediate GHC Core representation until it is in the desired normal form. The normalized Core/System Fc is then 'trivially' translated to RTL-style VHDL. The new version of CLaSH has the following updates: - Support for simulation and synthesis of multi-clock hardware [6] - Significant synthesis speed-up (4x to 10x) CLaSH already supported synthesis of: - User-defined Higher-Order functions [1] - User-defined ADTs (GADTs are not tested, but *might* work) - All of Haskell's choice constructs (Guards, Pattern Matching, etc.) - Lambda-abstraction / Anonymous Functions You can use CLaSH as a library, but the use of the adapted GHC interpreter (added the :vhdl command) is recommended. The interpreter can be found on the CLaSH website [2], where you will also find examples, papers, tutorials, etc. The library can be downloaded from Hackage [3]. I recently gave a demo of CLaSH at the DATE'11 conference in grenoble, this demo already made use of the multi-clock feature (and is actually the only reference if you want to experiment with multi-clock hardware yourself). The source for the demo (audio spectrum analyzer programmed on an Altera Cyclone II FPGA board) can be downloaded from my github page [4]. Do note that CLaSH only works when you have the 6.12.* branch of GHC installed! I am currently analyzing the impact of the GHC API changes made in the 7.0.* brach, and hope to make the transition to the new API within the next month. Although the compiler is already used by 2 other phd's in our group [5], it is not a thoroughly tested product, so your coding style might not be anticipated by the current version of CLaSH ;-) -- Christiaan Baaij [1] There is hard-coded support for a set of recursively defined higher-order functions such as map, fold, zipWith, etc. [2] http://clash.ewi.utwente.nl [3] http://hackage.haskell.org/package/clash-0.1.3.0 [4] http://github.com/christiaanb/DE1-Cyclone-II-FPGA-Board-Support-Package [5] http://caes.ewi.utwente.nl [6] Simulation does not show meta-stability, you will have to take care of synchronization (dual flipflop) yourself
I now also fixed the examples on the website [1] to work with version 0.1.3.0 of CLaSH :-) -- Christiaan [1] http://clash.ewi.utwente.nl On Mar 22, 2011, at 6:43 PM, Christiaan Baaij wrote:
Hello,
I am pleased to announce an incremental update to CLaSH, version 0.1.3.0.
CLaSH can translate a (semantic) subset of Haskell to RTL-style VHDL. Instead of being an embedded DSL like Lava or ForSyDe, CLaSH takes are more 'traditional' approach to synthesis/compilation. It uses the GHC API as a front-end for parsing, type-checking and desugaring the Haskell source. It then exhaustively applies a list of meaning-preserving transformations to the intermediate GHC Core representation until it is in the desired normal form. The normalized Core/System Fc is then 'trivially' translated to RTL-style VHDL.
The new version of CLaSH has the following updates: - Support for simulation and synthesis of multi-clock hardware [6] - Significant synthesis speed-up (4x to 10x)
CLaSH already supported synthesis of: - User-defined Higher-Order functions [1] - User-defined ADTs (GADTs are not tested, but *might* work) - All of Haskell's choice constructs (Guards, Pattern Matching, etc.) - Lambda-abstraction / Anonymous Functions
You can use CLaSH as a library, but the use of the adapted GHC interpreter (added the :vhdl command) is recommended. The interpreter can be found on the CLaSH website [2], where you will also find examples, papers, tutorials, etc. The library can be downloaded from Hackage [3].
I recently gave a demo of CLaSH at the DATE'11 conference in grenoble, this demo already made use of the multi-clock feature (and is actually the only reference if you want to experiment with multi-clock hardware yourself). The source for the demo (audio spectrum analyzer programmed on an Altera Cyclone II FPGA board) can be downloaded from my github page [4].
Do note that CLaSH only works when you have the 6.12.* branch of GHC installed! I am currently analyzing the impact of the GHC API changes made in the 7.0.* brach, and hope to make the transition to the new API within the next month. Although the compiler is already used by 2 other phd's in our group [5], it is not a thoroughly tested product, so your coding style might not be anticipated by the current version of CLaSH ;-)
-- Christiaan Baaij
[1] There is hard-coded support for a set of recursively defined higher-order functions such as map, fold, zipWith, etc. [2] http://clash.ewi.utwente.nl [3] http://hackage.haskell.org/package/clash-0.1.3.0 [4] http://github.com/christiaanb/DE1-Cyclone-II-FPGA-Board-Support-Package [5] http://caes.ewi.utwente.nl [6] Simulation does not show meta-stability, you will have to take care of synchronization (dual flipflop) yourself
Hello, Can you give some brief notes on the new introduced clock-related stuff like Comp? Thanks --Bin Jin On Wed, Mar 23, 2011 at 1:43 AM, Christiaan Baaij < christiaan.baaij@gmail.com> wrote:
Hello,
I am pleased to announce an incremental update to CLaSH, version 0.1.3.0.
CLaSH can translate a (semantic) subset of Haskell to RTL-style VHDL. Instead of being an embedded DSL like Lava or ForSyDe, CLaSH takes are more 'traditional' approach to synthesis/compilation. It uses the GHC API as a front-end for parsing, type-checking and desugaring the Haskell source. It then exhaustively applies a list of meaning-preserving transformations to the intermediate GHC Core representation until it is in the desired normal form. The normalized Core/System Fc is then 'trivially' translated to RTL-style VHDL.
The new version of CLaSH has the following updates: - Support for simulation and synthesis of multi-clock hardware [6] - Significant synthesis speed-up (4x to 10x)
CLaSH already supported synthesis of: - User-defined Higher-Order functions [1] - User-defined ADTs (GADTs are not tested, but *might* work) - All of Haskell's choice constructs (Guards, Pattern Matching, etc.) - Lambda-abstraction / Anonymous Functions
You can use CLaSH as a library, but the use of the adapted GHC interpreter (added the :vhdl command) is recommended. The interpreter can be found on the CLaSH website [2], where you will also find examples, papers, tutorials, etc. The library can be downloaded from Hackage [3].
I recently gave a demo of CLaSH at the DATE'11 conference in grenoble, this demo already made use of the multi-clock feature (and is actually the only reference if you want to experiment with multi-clock hardware yourself). The source for the demo (audio spectrum analyzer programmed on an Altera Cyclone II FPGA board) can be downloaded from my github page [4].
Do note that CLaSH only works when you have the 6.12.* branch of GHC installed! I am currently analyzing the impact of the GHC API changes made in the 7.0.* brach, and hope to make the transition to the new API within the next month. Although the compiler is already used by 2 other phd's in our group [5], it is not a thoroughly tested product, so your coding style might not be anticipated by the current version of CLaSH ;-)
-- Christiaan Baaij
[1] There is hard-coded support for a set of recursively defined higher-order functions such as map, fold, zipWith, etc. [2] http://clash.ewi.utwente.nl [3] http://hackage.haskell.org/package/clash-0.1.3.0 [4] http://github.com/christiaanb/DE1-Cyclone-II-FPGA-Board-Support-Package [5] http://caes.ewi.utwente.nl [6] Simulation does not show meta-stability, you will have to take care of synchronization (dual flipflop) yourself _______________________________________________ Haskell-Cafe mailing list Haskell-Cafe@haskell.org http://www.haskell.org/mailman/listinfo/haskell-cafe
Hi, The 'Comp' type is an automata arrow. In version 0.1.2.5 it was called 'Stat' [1], and was actually a newtype. The definition of Comp is:
data Comp i o = C { domain :: Set.Set Clock , exec :: Clock -> i -> (o, Comp i o) }
If you don't care about clock domains you can use the original lifting function (^^^) to lift transition functions to arrows. Below is an example that combines to multiply-accumulate circuits:
type Int8 = Signed D8
mac (State acc) (x,y) = (State (acc+x*y), acc)
dualMac :: Comp (Int8, Int8, Int8, Int8) Int8 dualMac = proc (a,b,c,d) -> do x <- mac ^^^ 0 -< (a,b) y <- mac ^^^ 0 -< (c,d) returnA -< (x+y)
If you do care about the clockdomain a component belongs to you use new multi-clock lifting function 'comp'. Below is an example of a component, 'keyboard' working in the keyboard clock domain, which is "20x slower" than the system clock. Also it responds to the 'falling' edge of the clock. The component that generates a sine-tone 'tonegeneration' runs at the system clock. There is also a synchronizing component 'synchronize' that runs at the system clock, using a dual flipflop, to synchronize the 'newKey' control value.
kbclock = ClockDown 20 sysclock = ClockUp 1
synthesizer :: Comp Bit (Signed D16) synthesizer = proc kbdata -> do (key,newKey) <- comp keyboard initkb kbclock -< kbdata newKS <- comp synchronize False sysclock -< newKey tone <- comp tonegeneration initTone sysclock -< (key,newKS) returnA -< tone
At the moment you shouldn't mix components created by the 'comp' function and the (^^^) function. The reason is that functions lifted with (^^^) would then basically operate in all introduced clock-domains when used in a multi-clock setting. You can use the simulateM function to simulate descriptions that use multiple clock domains. Example use of the simulateM function can be found in 'Testbench/AudioConfTest.hs' of our DATE'11 demo [2]. Available simulation statements for a simulation session can be found in 'CLasH/HardwareTypes.hs'. [3] As you might have figured out by now: our simulation of a multi-clock environment is not "truely" GALS. The clocks are certainly linked. For example, if you define:
clk1 = ClockUp 1 clk5 = ClockUp 5 clk20 = ClockUp 20
You could/should interpret it that clk1 has a period of 1ns, clk5 a
period of 5 ns, etc.
So clk1 runs 5 times faster than clk5, and clk5 runs 4 times faster than clk20.
As we can't simulate the effects of meta-stability, there is no
incentive for us to also give the clocks some decimal offset at this
point in the development of CLaSH.
I hope you have a better understanding of the multiple clock domain
stuff now :-)
Cheers,
Christiaan
[1] Marco Gerards, a PhD student from our group who originally
introduced Arrows in CLaSH, called it 'Stat' for reasons I no longer
know. We recently agreed that 'Comp', an abbreviation for 'Component',
is a more sensible name.
[2] http://github.com/christiaanb/DE1-Cyclone-II-FPGA-Board-Support-Package/blob...
[3] http://github.com/christiaanb/clash/blob/master/clash/CLasH/HardwareTypes.hs
On Fri, Mar 25, 2011 at 12:19 PM, Bin Jin
Hello, Can you give some brief notes on the new introduced clock-related stuff like Comp?
Thanks
--Bin Jin
participants (2)
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Bin Jin -
Christiaan Baaij