[posting on behalf of Ganesh <ganesh@cs.utah.edu>] Workshop on Multithreading in Hardware and Software: Formal Approaches to Design and Verification TV 2006 A FLoC'06 / CAV Affiliated Workshop August 21-22, 2006, Seattle, WA Scope of Workshop The use of threading is already widespread, and will experience explosive growth moving into the future, given that tomorrow's performance / energy goals will be met through the increased use of threads and "multicores" (chip level multiprocessors). Unfortunately, the correctness problems in this arena are daunting, as well as are far from being solved. TV06 invites papers addressing the tussle between correctness, reliability, and performance in this space. It is clear that well-engineered solutions in this space will require paying adequate attention to several areas, including (but clearly not limited to): * analysis, testing, and verification techniques for threaded systems * experience building reliable and high-performance threaded systems * case studies of verifying threaded systems * language design and formal semantics pertaining to threading * logics and models of concurrency, including transaction memories * model checking multithreaded programs * shared memory consistency models at the hardware, language, and library levels * runtime verification for multithreaded programs and systems * threading issues in multicore systems and chips * designing formally well-specified high-performance thread libraries * understanding threading issues in specific areas such as high-performance computing (e.g., OpenMP), general purpose libraries (e.g., PThreads), and languages (e.g., C#, Java) We invite researchers and engineers working on all aspects of threading, especially the above, to submit a paper as per specifications below. TV06 is hosted by the premier CAV conference, which is part of FLoC 2006 (Federated Logic Conference). which encompasses 6 conferences and over 30 workshops, and will be held in August in Seattle. Please visit http://research.microsoft.com/floc06 for a full description of these events, as well as a catchy poster. This location, setting, and timing promises ample opportunities for ample intellectual and social interactions. We especially welcome practitioners and system designers to describe a roadmap of priorities, given that many challenging problems need to be solved in short order. Invited Speakers * Vijay Saraswat, IBM T.J. Watson Research Labs, Yorktown Heights, NY * Maurice Herlihy, Brown University, Providence, RI Program Committee * Arvind MIT CSAIL, USA * Hans Boehm HP, USA * Ching Tsun Chou Intel,Santa Clara,USA * Byron Cook Microsoft Research, Cambridge,UK * Robert P. Cook Georgia Southern University, USA * Cormac Flanagan UC Santa Cruz, USA * Mike Kirby University of Utah, USA * Timothy G. Mattson Intel, DuPont, USA * John Regehr University of Utah, USA * Scott Stoller SUNY at Stony Brook, USA * Shaz Qadeer Microsoft Research, USA * Yue Yang Microsoft, USA Important Dates Deadline for submissions: May 1, 2006 Notification of acceptance: June 9, 2006 Final manuscript due: July 15, 2006 Workshop: August 21-22, 2006 Paper Submission Submissions must be made electronically in PDF format, following the instructions on the TV06 Web site, which is http://www.cs.utah.edu/tv06. Submissions must use the ACM SIG Proceedings format with letter-size paper (see http://www.acm.org/sigs/pubs/proceed/template.html for details). Two categories of papers will be accepted: * long : 10-15 pages, describing in-depth investigations * short: 4-6 pages, describing a tool, position statement, etc. Papers should contain a concise abstract of approximately 150 words, clearly stating the nature of the contributions. At least one author of each accepted paper is required to register for TV06 (registration information coming soon at http://www.cs.utah.edu/tv06) as well as give a presentation at the workshop. Papers should be self-contained, and describe original work, but may be based on (and may contain) portions from a previously published paper, provided it also includes substantial new work. A journal special issue based on selected papers from this workshop is under consideration. Email questions, if any, to tv06@cs.utah.edu Organizers Ganesh Gopalakrishnan, School of Computing, University of Utah, Salt Lake City, UT 84112, USA John W. O'Leary, Strategic CAD Labs, Intel Corporation, Hillsboro, OR, USA -- For questions and other information, please email tv06@cs.utah.edu or check http://www.cs.utah.edu/tv06 ---