It is widely spread convention to simulate electronic circuits using infinite lazy lists. This works well for high level modeling, but when engineers ask to cosimulate it with Verilog or VHDL modules it goes somewhat off of pure functional programming. The main obstacle is that those modules have their own internal state. Is it possible to represent a result of several impure calculation as a pure list? The only way I can think of is the use of unsafePerformIO. Maybe State monad will help? And how?