Sven Tennie pushed to branch wip/supersven/riscv-vectors at Glasgow Haskell Compiler / GHC Commits: f6705fd2 by Sven Tennie at 2025-06-28T17:58:23+02:00 Delete cruft - - - - - 463de889 by Sven Tennie at 2025-06-29T12:04:59+02:00 CheckVectorSupport: Support non-RVV cpus - - - - - 5 changed files: - − Makefile.save - − Notes.md - − ghc.diff - − git.diff - rts/CheckVectorSupport.c Changes: ===================================== Makefile.save deleted ===================================== @@ -1,13 +0,0 @@ -.PHONY: boot configure build test-simd000 - -boot: - ./boot - -configure: boot - configure_ghc - -build: - hadrian/build -j --docs=none --flavour=devel2 - -test-simd000: build - CROSS_EMULATOR="qemu-riscv64" hadrian/build -j --docs=none --flavour=devel2 test --only=simd000 ===================================== Notes.md deleted ===================================== @@ -1,7 +0,0 @@ -main.S: - -``` -v8 {q = {0xb0000000000000003}, l = {0x3, 0xb}, w = {0x3, 0x0, 0xb, 0x0}, s = {0x3, 0x0, 0x0, 0x0, 0xb, 0x0, 0x0, 0x0}, b = {0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xb, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}} -v10 {q = {0x1}, l = {0x1, 0x0}, w = {0x1, 0x0, 0x0, 0x0}, s = {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, b = {0x1, 0x0 }} - -``` ===================================== ghc.diff deleted ===================================== @@ -1,74 +0,0 @@ -diff --git a/compiler/CodeGen.Platform.h b/compiler/CodeGen.Platform.h -index 6f85686030..f91fee07fe 100644 ---- a/compiler/CodeGen.Platform.h -+++ b/compiler/CodeGen.Platform.h -@@ -1274,44 +1274,6 @@ freeReg REG_XMM5 = False - freeReg REG_XMM6 = False - # endif - --# if defined(REG_YMM1) --freeReg REG_YMM1 = False --# endif --# if defined(REG_YMM2) --freeReg REG_YMM2 = False --# endif --# if defined(REG_YMM3) --freeReg REG_YMM3 = False --# endif --# if defined(REG_YMM4) --freeReg REG_YMM4 = False --# endif --# if defined(REG_YMM5) --freeReg REG_YMM5 = False --# endif --# if defined(REG_YMM6) --freeReg REG_YMM6 = False --# endif -- --# if defined(REG_ZMM1) --freeReg REG_ZMM1 = False --# endif --# if defined(REG_ZMM2) --freeReg REG_ZMM2 = False --# endif --# if defined(REG_ZMM3) --freeReg REG_ZMM3 = False --# endif --# if defined(REG_ZMM4) --freeReg REG_ZMM4 = False --# endif --# if defined(REG_ZMM5) --freeReg REG_ZMM5 = False --# endif --# if defined(REG_ZMM6) --freeReg REG_ZMM6 = False --# endif -- - freeReg _ = True - - #else -diff --git a/compiler/GHC/CmmToAsm/RV64/Instr.hs b/compiler/GHC/CmmToAsm/RV64/Instr.hs -index bb4e0ba61c..ec00d5ef68 100644 ---- a/compiler/GHC/CmmToAsm/RV64/Instr.hs -+++ b/compiler/GHC/CmmToAsm/RV64/Instr.hs -@@ -20,7 +20,6 @@ import GHC.CmmToAsm.Utils - import GHC.Data.FastString (LexicalFastString) - import GHC.Platform - import GHC.Platform.Reg --import GHC.Platform.Reg.Class.Separate - import GHC.Platform.Regs - import GHC.Prelude - import GHC.Stack -diff --git a/compiler/GHC/CmmToAsm/RV64/Ppr.hs b/compiler/GHC/CmmToAsm/RV64/Ppr.hs -index 75cbcf2da6..2735bb5bef 100644 ---- a/compiler/GHC/CmmToAsm/RV64/Ppr.hs -+++ b/compiler/GHC/CmmToAsm/RV64/Ppr.hs -@@ -797,7 +797,7 @@ pprInstr platform instr = case instr of - FNMSub -> text "\tfnmsub" <> dot <> floatPrecission d - in op4 fma d r1 r2 r3 - VFMA variant o1@(OpReg fmt _reg) o2 o3 -- | VecFormat l fmt' <- fmt -> -+ | VecFormat _l fmt' <- fmt -> - let formatString = if (isFloatFormat . scalarFormatFormat) fmt' then text "f" else text "" - prefix = text "v" <> formatString - suffix = text "vv" ===================================== git.diff deleted ===================================== @@ -1,33 +0,0 @@ -diff --git a/testsuite/driver/cpuinfo.py b/testsuite/driver/cpuinfo.py -index 4617b04a4c..841ec9dfdc 100644 ---- a/testsuite/driver/cpuinfo.py -+++ b/testsuite/driver/cpuinfo.py -@@ -2151,6 +2152,10 @@ def _get_cpu_info_from_riscv_isa(): - seen.add(item) - return unique_list - -+ # Big endian is easier to head, but RISC-V is little endian -+ def bigToLittleEndian(w): -+ return int.from_bytes(w, byteorder='big').to_bytes(4, byteorder='little') -+ - g_trace.header('Tying to get info from device-tree ...') - - try: -@@ -2175,16 +2180,17 @@ def _get_cpu_info_from_riscv_isa(): - - if arch_string.startswith('rv32'): - vlen = run_asm( -- b"\xc2\x20\x25\x73", # csrr a0, 0xc22 -- b"\x00\x00\x80\x67" # ret -+ bigToLittleEndian(b"\xc2\x20\x25\x73"), # csrr a0, 0xc22 -+ bigToLittleEndian(b"\x00\x00\x80\x67") # ret - ) - elif arch_string.startswith('rv64'): - vlen = run_asm( -- b"\xc2\x20\x25\x73", # csrr a0, 0xc22 -- b"\x00\x05\x05\x1b", # sext.w a0, a0 -- b"\x00\x00\x80\x67" # ret -+ bigToLittleEndian(b"\xc2\x20\x25\x73"), # csrr a0, 0xc22 -+ bigToLittleEndian(b"\x00\x05\x05\x1b"), # sext.w a0, a0 -+ bigToLittleEndian(b"\x00\x00\x80\x67") # ret - ) ===================================== rts/CheckVectorSupport.c ===================================== @@ -4,10 +4,17 @@ #if defined(__riscv_v) && defined(__riscv_v_intrinsic) #include #include +#include +#include -// TODO: Find better file for this. -void* malloc_vlen_vector() { - return malloc(__riscv_vlenb()); +static jmp_buf jmpbuf; + +// Signal handler for SIGILL (Illegal Instruction) +static void sigill_handler(int); +static void sigill_handler(__attribute__((unused)) int sig) { + // If we get here, the vector instruction caused an illegal instruction + // exception. We just swallow it. + longjmp(jmpbuf, 1); } #endif @@ -74,11 +81,29 @@ int checkVectorSupport(void) { supports_V32 = hwcap & PPC_FEATURE_HAS_VSX; */ + // Detect RISC-V support #elif defined(__riscv_v) && defined(__riscv_v_intrinsic) // __riscv_v ensures we only get here when the compiler target (arch) // supports vectors. - - unsigned vlenb = __riscv_vlenb(); + // Unfortunately, the status registers that could tell about RVV support + // are part of the priviledged ISA. So, we try to get VLENB from the `vlenb` + // register that only exists with RVV. If this throws an illegal instruction + // exception, we know that RVV is not supported by the executing CPU. + + // Set up signal handler to catch illegal instruction + struct sigaction sa, old_sa; + sa.sa_handler = sigill_handler; + sigemptyset(&sa.sa_mask); + sa.sa_flags = 0; + sigaction(SIGILL, &sa, &old_sa); + + unsigned vlenb = 0; + if (setjmp(jmpbuf) == 0) { + // Try to execute a vector instruction + vlenb = __riscv_vlenb(); + } + // Restore original signal handler + sigaction(SIGILL, &old_sa, NULL); // VLENB gives the length in bytes supports_V16 = vlenb >= 16; View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/compare/7f5ae460efbb8513e80941fdeecea88... -- View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/compare/7f5ae460efbb8513e80941fdeecea88... You're receiving this email because of your account on gitlab.haskell.org.