Sven Tennie pushed to branch wip/supersven/riscv-vectors at Glasgow Haskell Compiler / GHC Commits: 2306dd0a by Sven Tennie at 2025-07-02T18:06:29+02:00 Fix CheckVectorSupport - - - - - 80263d35 by Sven Tennie at 2025-07-02T18:10:13+02:00 Always configure -march=rv64gcv - - - - - 5 changed files: - configure.ac - libraries/unix - + m4/fp_riscv_march.m4 - rts/CheckVectorSupport.c - utils/ghc-toolchain/src/GHC/Toolchain/Tools/Cc.hs Changes: ===================================== configure.ac ===================================== @@ -450,6 +450,8 @@ FP_SET_CFLAGS_C99([CC_STAGE0],[CONF_CC_OPTS_STAGE0],[CONF_CPP_OPTS_STAGE0]) FP_SET_CFLAGS_C99([CC],[CONF_CC_OPTS_STAGE1],[CONF_CPP_OPTS_STAGE1]) FP_SET_CFLAGS_C99([CC],[CONF_CC_OPTS_STAGE2],[CONF_CPP_OPTS_STAGE2]) +FP_RISCV_MARCH([CONF_CC_OPTS_STAGE2]) + dnl ** Do we have a compatible emsdk version? dnl -------------------------------------------------------------- EMSDK_VERSION("3.1.20", "", "") ===================================== libraries/unix ===================================== @@ -1 +1 @@ -Subproject commit 74ae1c0d9dd1518434f7d6cd3e63d7769599e0f9 +Subproject commit 47d5fc4a8f19207819030725e7de23c65fa61a04 ===================================== m4/fp_riscv_march.m4 ===================================== @@ -0,0 +1,34 @@ +dnl -------------------------------------------------------------------------- +dnl Set RISC-V architecture with vector extension (RVV) +dnl +dnl This macro checks if the target is RISC-V and if so, sets -march=rv64gcv / +dnl -march=rv32gcv (general, compressed, vector) to enable vector extension +dnl -------------------------------------------------------------------------- + +# FP_RISCV_MARCH(compiler_flags_var) +# ------------------------------------------ +# +# Example usage: +# FP_RISCV_MARCH([CONF_CC_OPTS_STAGE2]) +# +AC_DEFUN([FP_RISCV_MARCH], +[ + AC_REQUIRE([AC_CANONICAL_TARGET]) + + # Check if target is RISC-V + case "$target" in + riscv64*-*-*) + AC_MSG_NOTICE([add -march=rv64gcv to $1]) + + # Add vector extension flag to the specified variable + $1="$$1 -march=rv64gcv" + ;; + + riscv32*-*-*) + AC_MSG_NOTICE([add -march=rv64gcv to $1]) + + # Add vector extension flag to the specified variable + $1="$$1 -march=rv32gcv" + ;; + esac +]) ===================================== rts/CheckVectorSupport.c ===================================== @@ -14,7 +14,7 @@ static void sigill_handler(int); static void sigill_handler(__attribute__((unused)) int sig) { // If we get here, the vector instruction caused an illegal instruction // exception. We just swallow it. - longjmp(jmpbuf, 1); + siglongjmp(jmpbuf, 1); } #endif @@ -98,9 +98,9 @@ int checkVectorSupport(void) { sigaction(SIGILL, &sa, &old_sa); unsigned vlenb = 0; - if (setjmp(jmpbuf) == 0) { + if (sigsetjmp(jmpbuf, 1) == 0) { // Try to execute a vector instruction - vlenb = __riscv_vlenb(); + asm volatile("csrr %0, vlenb" : "=r" (vlenb) :: "memory"); } // Restore original signal handler sigaction(SIGILL, &old_sa, NULL); ===================================== utils/ghc-toolchain/src/GHC/Toolchain/Tools/Cc.hs ===================================== @@ -176,6 +176,8 @@ addPlatformDepCcFlags archOs cc0 = do -- On LoongArch64, we need `-mcmodel=medium` to tell gcc to generate big -- enough jump instruction. return $ cc1 & _ccFlags %++ "-mcmodel=medium" + ArchOS ArchRISCV64 _ -> + return $ cc1 & _ccFlags %++ "-march=rv64gcv" _ -> return cc1 View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/compare/bc674b5425666a0706b31f779061e36... -- View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/compare/bc674b5425666a0706b31f779061e36... You're receiving this email because of your account on gitlab.haskell.org.