July 2013 - ghc-tickets

Re: [GHC] #4001: Implement an atomic readMVar
by GHC 09 Jul '13

09 Jul '13

#4001: Implement an atomic readMVar ----------------------------+---------------------------------------------- Reporter: | Owner: ezyang simonmar | Status: closed Type: task | Milestone: 7.6.2 Priority: low | Version: 6.12.2 Component: Runtime | Keywords: System | Architecture: Unknown/Multiple Resolution: fixed | Difficulty: Moderate (less than a day) Operating System: | Blocked By: Unknown/Multiple | Related Tickets: Type of failure: | None/Unknown | Test Case: | Blocking: | ----------------------------+---------------------------------------------- Changes (by ezyang): * status: new => closed * resolution: => fixed Comment: {{{ commit 70e20631742e516c6a11c3c112fbd5b4a08c15ac Author: Edward Z. Yang <ezyang(a)mit.edu> Date: Mon Jul 8 11:03:35 2013 -0700 Implement atomicReadMVar, fixing #4001. We add the invariant to the MVar blocked threads queue that threads blocked on an atomic read are always at the front of the queue. This invariant is easy to maintain, since takers are only ever added to the end of the queue. Signed-off-by: Edward Z. Yang <ezyang(a)mit.edu> commit 1cb6aee7fd81175fe0af81146e878aaf7cda87d2 Author: Edward Z. Yang <ezyang(a)mit.edu> Date: Fri Jun 14 14:21:02 2013 -0700 Tests for atomicReadMVar. Signed-off-by: Edward Z. Yang <ezyang(a)mit.edu> commit c464def32f8ba65927ecfcbe34a5f06c21774ecc Author: Edward Z. Yang <ezyang(a)mit.edu> Date: Fri Jun 14 14:19:58 2013 -0700 Add atomicReadMVar to Control.Concurrent.MVar and friends. Also renumber thread statuses as necessary. Signed-off-by: Edward Z. Yang <ezyang(a)mit.edu> }}} -- Ticket URL: <http://ghc.haskell.org/trac/ghc/ticket/4001#comment:21> GHC <http://www.haskell.org/ghc/> The Glasgow Haskell Compiler

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Re: [GHC] #2507: quotation characters in error messages
by GHC 09 Jul '13

09 Jul '13

#2507: quotation characters in error messages -------------------------------------+------------------------------------ Reporter: Isaac Dupree | Owner: Type: feature request | Status: closed Priority: lowest | Milestone: 7.6.2 Component: Compiler | Version: 6.8.3 Resolution: fixed | Keywords: Operating System: Unknown/Multiple | Architecture: Unknown/Multiple Type of failure: None/Unknown | Difficulty: Unknown Test Case: | Blocked By: Blocking: | Related Tickets: #2811,#3398 -------------------------------------+------------------------------------ Comment (by refold): Replying to [comment:18 refold]: > Replying to [comment:17 igloo]: > > Done > > It looks like it's not possible to disable unicode quotes with `LANG=C` Looks like one must use `LC_ALL` instead. -- Ticket URL: <http://ghc.haskell.org/trac/ghc/ticket/2507#comment:19> GHC <http://www.haskell.org/ghc/> The Glasgow Haskell Compiler

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Re: [GHC] #8033: add AVX register support to llvm calling convention
by GHC 09 Jul '13

09 Jul '13

#8033: add AVX register support to llvm calling convention -------------------------------------+------------------------------------ Reporter: carter | Owner: carter Type: task | Status: new Priority: normal | Milestone: Component: Compiler | Version: 7.7 Resolution: | Keywords: Operating System: Unknown/Multiple | Architecture: Unknown/Multiple Type of failure: None/Unknown | Difficulty: Unknown Test Case: | Blocked By: Blocking: | Related Tickets: -------------------------------------+------------------------------------ Comment (by gmainland): I support a patch for x86_64 that passes 256-bit vectors in YMM registers when AVX is available. I am ambivalent about changing the x86_32 calling conventions, but it seems to me it would be a mistake to continue passing Float and Double arguments on the stack when SSE2 instructions are available. -- Ticket URL: <http://ghc.haskell.org/trac/ghc/ticket/8033#comment:27> GHC <http://www.haskell.org/ghc/> The Glasgow Haskell Compiler

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Re: [GHC] #2507: quotation characters in error messages
by GHC 09 Jul '13

09 Jul '13

#2507: quotation characters in error messages -------------------------------------+------------------------------------ Reporter: Isaac Dupree | Owner: Type: feature request | Status: closed Priority: lowest | Milestone: 7.6.2 Component: Compiler | Version: 6.8.3 Resolution: fixed | Keywords: Operating System: Unknown/Multiple | Architecture: Unknown/Multiple Type of failure: None/Unknown | Difficulty: Unknown Test Case: | Blocked By: Blocking: | Related Tickets: #2811,#3398 -------------------------------------+------------------------------------ Comment (by refold): Replying to [comment:17 igloo]: > Done It looks like it's not possible to disable unicode quotes with `LANG=C` (at least on my system, Ubuntu 12.04): {{{ $ env LANG=C ~/bin/ghc-head/bin/ghci Prelude GHC.IO.Encoding GHC.Foreign System.IO> let str = "‛’" > let enc = localeEncoding > (withCString enc str $ \cstr -> do { str' <- peekCString enc cstr; return (str == str') }) True }}} -- Ticket URL: <http://ghc.haskell.org/trac/ghc/ticket/2507#comment:18> GHC <http://www.haskell.org/ghc/> The Glasgow Haskell Compiler

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Re: [GHC] #8033: add AVX register support to llvm calling convention
by GHC 09 Jul '13

09 Jul '13

#8033: add AVX register support to llvm calling convention -------------------------------------+------------------------------------ Reporter: carter | Owner: carter Type: task | Status: new Priority: normal | Milestone: Component: Compiler | Version: 7.7 Resolution: | Keywords: Operating System: Unknown/Multiple | Architecture: Unknown/Multiple Type of failure: None/Unknown | Difficulty: Unknown Test Case: | Blocked By: Blocking: | Related Tickets: -------------------------------------+------------------------------------ Comment (by carter): Ok, so we should change the hasSSE1 to hasSSE2 to simplify adding short vector / simd support uniformly when its available (ie, for now NOT have 32bit ghc put floats and doubles in registers, thats something we can consider at some future point perhaps). So for now (a) {{{ // Pass in STG registers for floats, doubles and 128bit simd vectors CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>, // Pass in STG registers for 256bit simd vectors CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCIfSubtarget<"hasAVX()", CCAssignToReg<[ YMM1, YMM2, YMM3, YMM4, YMM5, YMM6]>>> }}} for x86_64 and {{{ // Pass in STG registers for floats, doubles and 128bit simd vectors CCIfType<[ v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>, // Pass in STG registers for 256bit simd vectors CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCIfSubtarget<"hasAVX()", CCAssignToReg<[ YMM1, YMM2, YMM3, YMM4, YMM5, YMM6]>>> }}} for x86_32? (though we could use the same stanza ) or (b) {{{ // Pass in STG registers for floats, doubles and 128bit simd vectors CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>, // Pass in STG registers for 256bit simd vectors CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCIfSubtarget<"hasAVX()", CCAssignToReg<[ YMM1, YMM2, YMM3, YMM4, YMM5, YMM6]>>> }}} for BOTH? (but not use the registers for floats and doubles in x86_32 for now) either change will be compatible with past and current GHCs -- Ticket URL: <http://ghc.haskell.org/trac/ghc/ticket/8033#comment:26> GHC <http://www.haskell.org/ghc/> The Glasgow Haskell Compiler

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Re: [GHC] #703: all binaries built by ghc have executable stacks
by GHC 09 Jul '13

09 Jul '13

#703: all binaries built by ghc have executable stacks ----------------------------+---------------------------------------------- Reporter: duncan | Owner: ezyang Type: merge | Status: merge Priority: normal | Milestone: 6.6.1 Component: | Version: 7.6.3 Compiler (NCG) | Keywords: Resolution: | Architecture: Unknown/Multiple Operating System: Linux | Difficulty: Moderate (less than a day) Type of failure: | Blocked By: None/Unknown | Related Tickets: Test Case: N/A | Blocking: | ----------------------------+---------------------------------------------- Comment (by simonmar): Thanks Edward! -- Ticket URL: <http://ghc.haskell.org/trac/ghc/ticket/703#comment:19> GHC <http://www.haskell.org/ghc/> The Glasgow Haskell Compiler

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Re: [GHC] #8033: add AVX register support to llvm calling convention
by GHC 09 Jul '13

09 Jul '13

#8033: add AVX register support to llvm calling convention -------------------------------------+------------------------------------ Reporter: carter | Owner: carter Type: task | Status: new Priority: normal | Milestone: Component: Compiler | Version: 7.7 Resolution: | Keywords: Operating System: Unknown/Multiple | Architecture: Unknown/Multiple Type of failure: None/Unknown | Difficulty: Unknown Test Case: | Blocked By: Blocking: | Related Tickets: -------------------------------------+------------------------------------ Comment (by gmainland): SSE2 instructions are always available on the 64-bit Intel architecture. -- Ticket URL: <http://ghc.haskell.org/trac/ghc/ticket/8033#comment:25> GHC <http://www.haskell.org/ghc/> The Glasgow Haskell Compiler

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Re: [GHC] #8033: add AVX register support to llvm calling convention
by GHC 09 Jul '13

09 Jul '13

#8033: add AVX register support to llvm calling convention -------------------------------------+------------------------------------ Reporter: carter | Owner: carter Type: task | Status: new Priority: normal | Milestone: Component: Compiler | Version: 7.7 Resolution: | Keywords: Operating System: Unknown/Multiple | Architecture: Unknown/Multiple Type of failure: None/Unknown | Difficulty: Unknown Test Case: | Blocked By: Blocking: | Related Tickets: -------------------------------------+------------------------------------ Comment (by carter): @gmainland, is the sse2 test always true on x86_64? Thats my concern, that -msse on x86_64 will be "wrong" with GHC head now that we have SIMD support. Unless LLVM does the right instruction lowering / register transfers when trying to use sse2 when set to -msse -- Ticket URL: <http://ghc.haskell.org/trac/ghc/ticket/8033#comment:24> GHC <http://www.haskell.org/ghc/> The Glasgow Haskell Compiler

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Re: [GHC] #8033: add AVX register support to llvm calling convention
by GHC 09 Jul '13

09 Jul '13

#8033: add AVX register support to llvm calling convention -------------------------------------+------------------------------------ Reporter: carter | Owner: carter Type: task | Status: new Priority: normal | Milestone: Component: Compiler | Version: 7.7 Resolution: | Keywords: Operating System: Unknown/Multiple | Architecture: Unknown/Multiple Type of failure: None/Unknown | Difficulty: Unknown Test Case: | Blocked By: Blocking: | Related Tickets: -------------------------------------+------------------------------------ Comment (by gmainland): I have way to much on my plate at the moment to do anything other than answer questions, although I am happy to do that. The hasSSE1 test is vacuously true on x86_64. So it doesn't affect code correctness, but it is confusing. I was wrong about needing the test at all on x32. We could make GHC pass Floats and Double on the stack when SSE is off, pass Floats in registers when -msse is set, and pass both Floats and Doubles (an vectors) in registers when -msse2 is set. The test wouldn't be necessary, because if -msse2 isn't set, GHC will simply pass Doubles on the stack and LLVM will never see a function call with a double-precision argument. I'm not concerned with 32-bit performance at this point. Do you have an application that requires these changes for performance reasons? If you do, I still don't think it's worth making changes to the 32-bit LLVM calling conventions until we can utilize them in GHC. Simply changing the GHC calling convention in LLVM isn't enough, even when using the LLVM back-end. -- Ticket URL: <http://ghc.haskell.org/trac/ghc/ticket/8033#comment:23> GHC <http://www.haskell.org/ghc/> The Glasgow Haskell Compiler

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Re: [GHC] #8033: add AVX register support to llvm calling convention
by GHC 09 Jul '13

09 Jul '13

#8033: add AVX register support to llvm calling convention -------------------------------------+------------------------------------ Reporter: carter | Owner: carter Type: task | Status: new Priority: normal | Milestone: Component: Compiler | Version: 7.7 Resolution: | Keywords: Operating System: Unknown/Multiple | Architecture: Unknown/Multiple Type of failure: None/Unknown | Difficulty: Unknown Test Case: | Blocked By: Blocking: | Related Tickets: -------------------------------------+------------------------------------ Comment (by carter): 1. changing to "hasSSE2()" will make the engineering for the various levels of SIMD and impact on calling convention a teenyt bit simpler a. If we keep "hasSSE1", we'll want to spill Double's to the stack at -msse1, and pass the first few in registers on -msse2 or higher, which is easy for us to support because we do our stack spills and loads *BEFORE* llvm. This is because SSE1 only supports operations on Floats and not Doubles. (@gmainland, I see you replied already) b. yes, as GHC's SIMD is currently implemented, this is a bug in LLVM (or an oversight on our side?!). @Gmainland, could you create a ticket with a toy example using GHC head that illustrates it as a bug? (LLVM patches that are bug fixes for down stream tools are things we can get considered for the 3.3 POINT release). having a ticket and an explicit example that hits it would be handy! 2. The same sort of instruction selection/register problem sort of happens once we consider supporting both AVX1 and AVX2! a. AVX1 only supports 256bit Float / Double short vector operations, its Word / Int operations are 128bit only. b. AVX2 is required for Word / Int operations to be 256bit (except when you can encode them as the corresponding Floating point SIMD operations). So we really need to sort out a good story here for that anyways (which is kinda the same or similar to the sse1 vs sse2 problem, Ie many machines have AVX1, all sandy-bridge and ivy-bridge Intel chips, and only some cpus have AVX2, the recent Haswell generation) 3. (this perhaps should be done as a different patch for llvm) Would it be worth considering augmenting the number of XMM / YMM used to be''' XMM0-7/YMM0-7''' ? (from current XMM1-6 ). This would be the same scope of change as the x86_32 specific change, but would mean that roughy LLVM 3.4 onwards would only work with newer ghcs. (this is true anyways actually right? 7.6 and earlier are a bit sloppier in their generated bit code, so they dont play nice with newest llvm's, right? ). a. This wouldn't change any Caller side code except for stack spilling, and any calle side code aside from a few reads from the stack, right? should I re-email the list to make sure other folks are in the loop? It sounds like we're already considering changing the x86_32 calling convention (albeit in a ghc old and new compatible way), and thats as good a time as any to start seriously considering any other calling convention changes, even if we test them out using a patched GHC and LLVM first. (i don't have the right hardware to run NOFIB for testing such a change myself...) -- Ticket URL: <http://ghc.haskell.org/trac/ghc/ticket/8033#comment:22> GHC <http://www.haskell.org/ghc/> The Glasgow Haskell Compiler

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