I'd like to let dear readers to know that I finally managed to put source code and some documentation related to modeling of digital circuits and whole systems. Most of the work was done in 2006 and 2007, so this is very old news. But I finally found time to put everything in more-or-less usable state and put it online (thanks to Max Taldykin, the host of Moskow HUG). I put it online a while ago so this is just old news. The SVN repository is here: http://thesz.mskhug.ru/browser/hiersort This is the model of multicore dynamic dataflow machine (with a twist), the draft paper about architecture under consideration and a presentation about the use of Haskell in modeling (almost) complete MIPS CPU with memory. The core of our modeling framework is here: http://thesz.mskhug.ru/browser/hiersort/core/S.hs The paper about dataflow machine is here: http://thesz.mskhug.ru/browser/hiersort/doc/sdd2.pdf And the presentation is here: http://thesz.mskhug.ru/browser/hiersort/doc/hhm-eng.pdf To summarize presentation content: we were able to deliver working model of MIPS CPU with working model of dynamic memory with memory controller in four months. The biggest roadblock encountered is the memory leak we couldn't get rid of. We often use Haskell to prototype various kinds of IP blocks and (parts of) computer architecture since that.